package hardcaml

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package hardcaml
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type task = unit -> unit
type !'a cyclesim = 'a Cyclesim.Api.cyclesim = {
  1. sim_in_ports : (string * 'a Stdlib.ref) list;
  2. sim_out_ports : (string * 'a Stdlib.ref) list;
  3. sim_out_ports_next : (string * 'a Stdlib.ref) list;
  4. sim_internal_ports : (string * 'a Stdlib.ref) list;
  5. sim_reset : task;
  6. sim_cycle_check : task;
  7. sim_cycle_comb0 : task;
  8. sim_cycle_seq : task;
  9. sim_cycle_comb1 : task;
  10. sim_lookup_signal : Signal.Types.uid -> 'a Stdlib.ref;
  11. sim_lookup_reg : Signal.Types.uid -> 'a Stdlib.ref;
  12. sim_lookup_memory : Signal.Types.uid -> 'a array;
}
val cycle : 'a cyclesim -> unit
val cycle_check : 'a cyclesim -> unit
val cycle_comb0 : 'a cyclesim -> unit
val cycle_seq : 'a cyclesim -> unit
val cycle_comb1 : 'a cyclesim -> unit
val reset : 'a cyclesim -> unit
val in_port : 'a cyclesim -> string -> 'a Stdlib.ref
val out_port : 'a cyclesim -> string -> 'a Stdlib.ref
val out_port_next : 'a cyclesim -> string -> 'a Stdlib.ref
val internal_port : 'a cyclesim -> string -> 'a Stdlib.ref
val in_ports : 'a cyclesim -> (string * 'a Stdlib.ref) list
val out_ports : 'a cyclesim -> (string * 'a Stdlib.ref) list
val out_ports_next : 'a cyclesim -> (string * 'a Stdlib.ref) list
val internal_ports : 'a cyclesim -> (string * 'a Stdlib.ref) list
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