package hardcaml

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package hardcaml
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Library
Module
Module type
Parameter
Class
Class type
type t =
  1. | U
    (*

    Uninitialized

    *)
  2. | X
    (*

    Unknown

    *)
  3. | L0
    (*

    Logic 0

    *)
  4. | L1
    (*

    Logic 1

    *)
  5. | Z
    (*

    High impedance

    *)
  6. | W
    (*

    Weak - neither prefer 0 or 1

    *)
  7. | L
    (*

    Weak - prefer 0

    *)
  8. | H
    (*

    Weak - prefer 1

    *)
  9. | Don't_care
    (*

    Dont care

    *)
include Ppx_compare_lib.Comparable.S with type t := t
val compare : t -> t -> int
include Ppx_enumerate_lib.Enumerable.S with type t := t
val all : t list
include Sexplib0.Sexpable.S with type t := t
val t_of_sexp : Sexplib0.Sexp.t -> t
val sexp_of_t : t -> Sexplib0.Sexp.t
val u : t
val x : t
val l0 : t
val l1 : t
val z : t
val w : t
val l : t
val h : t
val don't_care : t
val is_u : t -> Base.bool
val is_x : t -> Base.bool
val is_l0 : t -> Base.bool
val is_l1 : t -> Base.bool
val is_z : t -> Base.bool
val is_w : t -> Base.bool
val is_l : t -> Base.bool
val is_h : t -> Base.bool
val is_don't_care : t -> Base.bool
val u_val : t -> Base.unit Base.option
val x_val : t -> Base.unit Base.option
val l0_val : t -> Base.unit Base.option
val l1_val : t -> Base.unit Base.option
val z_val : t -> Base.unit Base.option
val w_val : t -> Base.unit Base.option
val l_val : t -> Base.unit Base.option
val h_val : t -> Base.unit Base.option
val don't_care_val : t -> Base.unit Base.option
module Variants : sig ... end
include Base.Equal.S with type t := t
val equal : t Base.Equal.equal
val to_int : t -> Base.int

Provide the index of t in textual order. When passing a std_logic parameter from verilog to vhdl, we need to encode this type into an integer. For example, L1 = 4'd3.

val of_char_exn : Base.char -> t

The OCaml char used in of_char and to_char is the same as used in VHDL.

val to_char : t -> Base.char
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