package hardcaml

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package hardcaml
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Module
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Class type
type t = {
  1. detect_combinational_loops : Base.bool;
    (*

    Check circuit for combinational loops (cyclic paths that do not pass through a register or memory).

    *)
  2. normalize_uids : Base.bool;
    (*

    Renumber the Uids of all signals in the circuit starting at one.

    Uid normalization ensures that circuits will print the same (as sexps or rtl) regardless of the environment in which they are constructed (in particular with regard to the global uid generator).

    *)
  3. assertions : Hardcaml__.Assertion_manager.t Base.option;
  4. port_checks : Port_checks.t;
    (*

    Perform validation checks on inputs and outputs (With_interface only)

    *)
  5. add_phantom_inputs : Base.bool;
    (*

    Add inputs defined in an Interface but not used within the Circuit (With_interface only).

    *)
  6. modify_outputs : Signal.t Base.list -> Signal.t Base.list;
    (*

    Map over circuit outputs just before constructing the circuit.

    *)
}
val default : t

Perform combinational loop checks, uid normalization, strict port checks, and add phantom inputs.

val default_for_simulations : t

Deftault checks for simulations. Drop combinational loop checks (the simulation scheduler will do that anyway) and uid normalization. Used by Cyclesim.With_interface.

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