package hardcaml_xilinx

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package hardcaml_xilinx
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Source file ram_port.ml

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open! Base
open! Hardcaml

type 'a t =
  { address : 'a
  ; data : 'a
  ; read_enable : 'a
  ; write_enable : 'a
  }
[@@deriving sexp_of, hardcaml]