Source file hardcaml_xilinx.ml

module Byte_write_width = Byte_write_width
module Cascade_height = Cascade_height
module Collision_mode = Collision_mode
module Ram_arch = Ram_arch
module Dual_port_ram = Dual_port_ram
module Fifo_async = Fifo_async
module Fifo_sync = Fifo_sync
module Simple_dual_port_ram = Simple_dual_port_ram
module True_dual_port_ram = True_dual_port_ram
module Ram_port = Ram_port
module Ram_port_with_clear = Ram_port_with_clear
module Synthesis = Synthesis
module Memory_builder = Memory_builder