package hardcaml_xilinx

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package hardcaml_xilinx
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Configuration for the memory builder. See documentation below for elaboration about the purpose of configuration fields.

type inferred_memory = {
  1. rtl_attributes : Hardcaml.Rtl_attribute.t Base.list Base.option;
  2. rw_order : [ `Wbr | `Rbw ];
}
val sexp_of_inferred_memory : inferred_memory -> Sexplib0.Sexp.t
type how_to_instantiate_ram =
  1. | Xpm of Ram_arch.t
  2. | Inferred of inferred_memory
val sexp_of_how_to_instantiate_ram : how_to_instantiate_ram -> Sexplib0.Sexp.t
type underlying_memory = {
  1. data_width : Base.int;
  2. cascade_height : Cascade_height.t;
  3. how_to_instantiate_ram : how_to_instantiate_ram;
  4. simulation_name : Base.string Base.option;
}
type t = {
  1. underlying_memories : underlying_memory Base.list;
  2. underlying_ram_read_latency : Base.int;
  3. vertical_dimension : Base.int;
  4. horizontal_dimension : Base.int;
  5. combinational_output : Base.bool;
}
val vertical_dimension : t -> Base.int

The size of the outermost inner dimension. ie: shape1

val horizontal_index_width : t -> Base.int

The bit width for the horizontal dimension. Note that this will return 0 when the appropriate dimension is zero.

val vertical_index_width : t -> Base.int

Similar to horizontal_index_width, but for the vertical index

val read_latency : t -> Base.int

Equivalent to underlying_ram_read_latency + if combinational_output then 1 else 0

val create_simple_1d_config : depth:Base.int -> num_bits_per_entry:Base.int -> ram_read_latency:Base.int -> how_to_instantiate_ram:how_to_instantiate_ram -> simulation_name:Base.string Base.option -> t

Create the simplest possible 1D configuration with a single RAM architecture.

module type S = sig ... end
val as_module : t -> (module S)
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