package hardcaml_of_verilog

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hardcaml_of_verilog
- CHANGES
- LICENSE
- README
- Library hardcaml_of_verilog
  - Hardcaml_of_verilog
    
    Circuit_to_json
    
    Netlist
    
    Bit
    
    Bus
    
    Parameter
    
    Port
    
    Cell
    
    Bus_names
    
    Module
    
    Ocaml_module
    
    Rebuild_interfaces
    
    I
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    O
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Pass
    
    Verilog_circuit
    
    Port
    
    Verilog_design
    
    Parameter
    
    Parameters
    
    Define_value
    
    Define
    
    Defines
    
    Module
    
    Crunched
    
    Embedded_files
    
    With_interface
    
    Make
    
    Expert
    
    Synthesize
    
    Yosys_netlist
    
    Assoc_list
    
    Assoc_list
    
    Int_or_string
    
    Direction
    
    Bit
    
    Port
    
    V
    
    Parameter
    
    V
    
    Connection
    
    V
    
    Port_direction
    
    V
    
    Cell
    
    V
    
    Netname
    
    V
    
    Module
    
    V
- Library hardcaml_of_verilog.port
  - Hardcaml_port_verilog
    
    Make
- Sources
  - hardcaml_of_verilog
    
    circuit_bus_map.ml
    
    circuit_to_json.ml
    
    config.ml
    
    hardcaml_of_verilog.ml
    
    hardcaml_of_verilog__.ml
    
    lvt.ml
    
    netlist.ml
    
    ocaml_module.ml
    
    pass.ml
    
    synthesize.ml
    
    techlib.ml
    
    verilog_circuit.ml
    
    verilog_design.ml
    
    with_interface.ml
    
    yosys_netlist.ml
  - hardcaml_of_verilog.port
    
    hardcaml_port_verilog.ml
    
    hardcaml_port_verilog__.ml
    
    port_verilog.ml

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Module `Hardcaml_of_verilog.Verilog_design`Source

Sourcemodule Parameter : sig ... end

Sourcemodule Parameters : sig ... end

Sourcemodule Define_value : sig ... end

Sourcemodule Define : sig ... end

Sourcemodule Defines : sig ... end

Sourcemodule Module : sig ... end

Sourcetype t

include Sexplib0.Sexpable.S with type t := t

Sourceval t_of_sexp : Sexplib0.Sexp.t -> t

Sourceval sexp_of_t : t -> Sexplib0.Sexp.t

Sourceval create : ?defines:Defines.t -> top:Module.t -> Base.unit -> t

Sourceval defines : t -> Defines.t

Sourceval top : t -> Module.t

Sourceval top_name : t -> Base.string

Name of top level module

Sourceval override_parameters : t -> Parameters.t -> t

Override the parameters of the top level module

Sourceval map_paths : t -> f:(Base.string -> Base.string) -> t

map_paths t ~f applies f to each modules path

Sourcemodule type Crunched = sig ... end

Source

val map_crunched_paths : 
  ?delete_temp_files:Base.bool ->
  (module Crunched) Base.list ->
  t ->
  t

Read verilog files from ocaml-cruched file system(s) and extract to temp files.

Sourcemodule type Embedded_files = sig ... end

Source

val map_embed_file_paths : 
  ?delete_temp_files:Base.bool ->
  (module Embedded_files) Base.list ->
  t ->
  t

Read verilog files from embed_file file system(s) and extract to temp files.

package hardcaml_of_verilog

Module Hardcaml_of_verilog.Verilog_designSource

Module `Hardcaml_of_verilog.Verilog_design`Source