package hardcaml_of_verilog

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package hardcaml_of_verilog
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Module Verilog_design.Define_valueSource

Sourcetype t =
  1. | String of Base.string
  2. | Int of Base.int
  3. | No_arg
include Sexplib0.Sexpable.S with type t := t
Sourceval t_of_sexp : Sexplib0.Sexp.t -> t
Sourceval sexp_of_t : t -> Sexplib0.Sexp.t
include Ppx_compare_lib.Equal.S with type t := t
Sourceval equal : t -> t -> bool
Sourceval to_string : t -> Base.string
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