package hardcaml_of_verilog

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hardcaml_of_verilog
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- Library hardcaml_of_verilog
  - Hardcaml_of_verilog
    
    Circuit_to_json
    
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- Library hardcaml_of_verilog.port
  - Hardcaml_port_verilog
    
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  - hardcaml_of_verilog
    
    circuit_bus_map.ml
    
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    hardcaml_of_verilog.ml
    
    hardcaml_of_verilog__.ml
    
    lvt.ml
    
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    ocaml_module.ml
    
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    techlib.ml
    
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    verilog_design.ml
    
    with_interface.ml
    
    yosys_netlist.ml
  - hardcaml_of_verilog.port
    
    hardcaml_port_verilog.ml
    
    hardcaml_port_verilog__.ml
    
    port_verilog.ml

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Module `Verilog_design.Parameters`Source

Sourcetype t = Parameter.t Base.list

include Sexplib0.Sexpable.S with type t := t

Sourceval t_of_sexp : Sexplib0.Sexp.t -> t

Sourceval sexp_of_t : t -> Sexplib0.Sexp.t

Sourceval replace : t -> with_:t -> t

package hardcaml_of_verilog

Module Verilog_design.ParametersSource

Module `Verilog_design.Parameters`Source