package hardcaml_of_verilog

  1. Overview
  2. Docs
Convert Verilog to a Hardcaml design

Install

Dune Dependency

github.com Readme Changelog MIT License Edit opam file Versions (2)

Authors

  1. J
    Jane Street Group, LLC

Maintainers

  1. J
    Jane Street developers

Sources

hardcaml_of_verilog-v0.16.0.tar.gz
sha256=d0c73140e80b48f7e971d6fa94e7f8ed8aa64cd7685d0fb442eb590ba6a244b4

CHANGES.md.html

Release v0.16.0

  • Add a wrapper library called hardcaml_port_verilog which wraps the boilerplate code needed to write a Hardcaml equivalent to a verilog circuit and have it formally checked by hardcaml_verify.