package hardcaml_of_verilog
Convert Verilog to a Hardcaml design
Install
Authors
Maintainers
Sources
hardcaml_of_verilog-v0.16.0.tar.gz
sha256=d0c73140e80b48f7e971d6fa94e7f8ed8aa64cd7685d0fb442eb590ba6a244b4
CHANGES.md.html
Release v0.16.0
Add a wrapper library called hardcaml_port_verilog which wraps the boilerplate code needed to write a Hardcaml equivalent to a verilog circuit and have it formally checked by hardcaml_verify.
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