package hardcaml_event_driven_sim

  1. Overview
  2. Docs
package hardcaml_event_driven_sim
Legend:
Library
Module
Module type
Parameter
Class
Class type

Parameters

Signature

module Input : sig ... end
module Output : sig ... end
module Logic : sig ... end
module Ops : sig ... end
type t = {
  1. processes : Event_driven_sim.Simulator.Process.t list;
  2. input : Logic.t Port.t Input.t;
  3. output : Logic.t Port.t Output.t;
  4. internal : Logic.t Port.t list;
}
val create_clock : ?initial_delay:int -> time:int -> Logic.t Event_driven_sim.Simulator.Signal.t -> Event_driven_sim.Simulator.Process.t
val create : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> t
type testbench = {
  1. ports_and_processes : t;
  2. simulator : Event_driven_sim.Simulator.t;
}
val with_processes : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> testbench
val with_vcd : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> vcd:Core.Out_channel.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> testbench
val with_waveterm : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> Waveterm.Waveform.t * testbench
val expect : ?config:Hardcaml_event_driven_sim__With_interface_intf.Config.t -> ?vcd:string -> Hardcaml.Interface.Create_fn(Input)(Output).t -> testbench_processes -> testbench
OCaml

Innovation. Community. Security.

GitHub Discord Twitter Peertube RSS
About
Changelog Releases Industrial Users Academic Users Why OCaml
Ecosystem
Packages Community Events OCaml Planet Jobs
Resources
Install OCaml Get Started Platform Tools Language Manual Standard Library API Books Exercises Papers OCaml Playground Logo
Policies
Carbon Footprint Governance Privacy Code of Conduct