package hardcaml_circuits

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package hardcaml_circuits
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Represents a computation broken into multiple stages. Each stage is returned in an array.

Used to implement generic register pipelining structures.

type 'a t = {
  1. input : 'a;
  2. output : 'a;
}
val sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t
type 'a stage_fn = Base.int -> 'a -> 'a

Function called to construct each stage. It receives the current stage index, the output from the previous stage and produces the next stage input.

val create : Base.int -> init:'a -> f:'a stage_fn -> 'a t Base.array

Create an array of stages. The returned array carries both the input and output data for each stage.

val input : 'a t Base.array -> 'a

The initial input of the stages construction.

val output : 'a t Base.array -> 'a

The final output of the stages construction.

Create a pipeline of registers. The enable controls the whole pipeline.

type enabled_stage = {
  1. enable : Hardcaml.Signal.t;
  2. data : Hardcaml.Signal.t;
}

Create a pipeline of registers. The enable is passed down the pipeline with the data.