package hardcaml
RTL Hardware Design in OCaml
Install
Authors
Maintainers
Sources
hardcaml-v0.16.0.tar.gz
sha256=1cc136550365918c5e72db328acf7bbf109f680bdacb60edb80972dee042a58d
Description
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Published: 14 Jun 2023
Dependencies (11)
-
zarith
>= "1.11"
-
ppxlib
>= "0.28.0"
-
dune
>= "2.0.0"
-
topological_sort
>= "v0.16" & < "v0.17"
-
stdio
>= "v0.16" & < "v0.17"
-
ppx_sexp_conv
>= "v0.16" & < "v0.17"
-
ppx_jane
>= "v0.16" & < "v0.17"
-
core_kernel
>= "v0.16" & < "v0.17"
-
bin_prot
>= "v0.16" & < "v0.17"
-
base
>= "v0.16" & < "v0.17"
-
ocaml
>= "4.14.0"
Dev Dependencies
Used by (14)
- hardcaml_axi
-
hardcaml_c
>= "v0.16.0"
-
hardcaml_circuits
>= "v0.16.0"
-
hardcaml_fixed_point
>= "v0.16.0"
- hardcaml_handshake
-
hardcaml_of_verilog
>= "v0.16.0"
-
hardcaml_step_testbench
>= "v0.16.0"
-
hardcaml_verify
>= "v0.16.0"
-
hardcaml_verilator
>= "v0.16.0"
-
hardcaml_waveterm
>= "v0.16.0"
-
hardcaml_xilinx
>= "v0.16.0"
-
hardcaml_xilinx_components
>= "v0.16.0"
- hardcaml_xilinx_reports
-
ppx_deriving_hardcaml
>= "v0.16.0"
Conflicts
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