package hardcaml

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package hardcaml
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Module Ram.Write_portSource

Sourcetype t = Signal.write_port = {
  1. write_clock : Signal.t;
  2. write_address : Signal.t;
  3. write_enable : Signal.t;
  4. write_data : Signal.t;
}
Sourceval sexp_of_t : t -> Sexplib0.Sexp.t