package hardcaml

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package hardcaml
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Module
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Class
Class type
type signal = Hardcaml__.Signal__type.t
type t = Hardcaml__.Signal__type.register = {
  1. reg_clock : signal;
  2. reg_clock_edge : Edge.t;
  3. reg_reset : signal;
  4. reg_reset_edge : Edge.t;
  5. reg_reset_value : signal;
  6. reg_clear : signal;
  7. reg_clear_level : Level.t;
  8. reg_clear_value : signal;
  9. reg_enable : signal;
}
val sexp_of_t : t -> Sexplib0.Sexp.t
val create : ?clear:signal -> ?reset:signal -> unit -> clock:signal -> t
val override : ?clock:signal -> ?clock_edge:Edge.t -> ?reset:signal -> ?reset_edge:Edge.t -> ?reset_to:signal -> ?clear:signal -> ?clear_level:Level.t -> ?clear_to:signal -> ?global_enable:signal -> t -> t
val reg_empty : t
val clock : t -> signal
val clear : t -> signal
val reset : t -> signal
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