HardCamlYosys.Techlib.Simlib.Dffe.I · hardcaml-yosys 0.1.0 · OCaml Packages

hardcaml-yosys

Import Verilog designs into HardCaml

package hardcaml-yosys

HardCamlYosys
- HardCamlYosys
  - Cell
  - Import
    
    I
    
    S
  - Io
  - Lvt
    
    Cfg
    
    Make
    
    1-C
    
    Rd
    
    Wr
    
    Make_wren
    
    1-C
    
    Rd
    
    Wr
    
    Multiport_regs
    
    1-C
    
    Rd
    
    Wr
    
    Rd
    
    Wr
  - Techlib
    
    Proof
    
    Cells
    
    I
    
    O
    
    P
    
    W
    
    Make
    
    1-C
    
    I
    
    O
    
    P
    
    W
    
    Simlib
    
    Adff
    
    I
    
    O
    
    P
    
    W
    
    Concat
    
    I
    
    O
    
    P
    
    W
    
    Dff
    
    I
    
    O
    
    P
    
    W
    
    Dffe
    
    I
    
    O
    
    P
    
    W
    
    Dffsr
    
    I
    
    O
    
    P
    
    W
    
    Fa
    
    I
    
    O
    
    P
    
    W
    
    Lcu
    
    I
    
    O
    
    P
    
    W
    
    Lut
    
    I
    
    O
    
    P
    
    W
    
    Mem
    
    I
    
    O
    
    P
    
    W
    
    Memrd
    
    I
    
    O
    
    P
    
    W
    
    Memwr
    
    I
    
    O
    
    P
    
    W
    
    Mux
    
    I
    
    O
    
    P
    
    W
    
    Op1
    
    I
    
    O
    
    P
    
    W
    
    Op2
    
    I
    
    O
    
    P
    
    W
    
    Pmux
    
    I
    
    O
    
    P
    
    W
    
    Slice
    
    I
    
    O
    
    P
    
    W
    
    Wrapper
    
    1-P
    
    2-I
    
    3-O
  - Yosys_atd_j
  - Yosys_atd_t

Legend:
Library
Module
Module type
Parameter
Class
Class type

Library HardCamlYosys

Module HardCamlYosys . Techlib . Simlib . Dffe . I

type !'a t = {

clk : 'a;

en : 'a;

d : 'a;

}

val t : (string * int) t

val map : ( 'a -> 'b ) -> 'a t -> 'b t

val map2 : ( 'a -> 'b -> 'c ) -> 'a t -> 'b t -> 'c t

val to_list : 'a t -> 'a list