package hardcaml
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RTL Hardware Design in OCaml
Install
dune-project
Dependency
Authors
Maintainers
Sources
v0.17.0.tar.gz
sha256=925bbc1f25dabcdea9cd6dc484badf689dc5dd18e511b6d105c4d7582cb29237
Description
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Published: 26 May 2024
Dependencies (10)
-
zarith
>= "1.11" -
ppxlib
>= "0.28.0" & < "0.36.0" -
dune
>= "3.11.0" -
stdio
>= "v0.17" & < "v0.18" -
ppx_sexp_conv
>= "v0.17" & < "v0.18" -
ppx_jane
>= "v0.17" & < "v0.18" -
core_kernel
>= "v0.17" & < "v0.18" -
bin_prot
>= "v0.17" & < "v0.18" -
base
>= "v0.17" & < "v0.18" -
ocaml
>= "5.1.0"
Dev Dependencies
None
Used by (16)
- hardcaml-lua
-
hardcaml_axi
>= "v0.17.0" -
hardcaml_c
>= "v0.17.0" -
hardcaml_circuits
>= "v0.17.0" - hardcaml_event_driven_sim
-
hardcaml_fixed_point
>= "v0.17.0" -
hardcaml_handshake
>= "v0.17.0" -
hardcaml_of_verilog
>= "v0.17.0" -
hardcaml_step_testbench
>= "v0.17.0" -
hardcaml_verify
>= "v0.17.0" -
hardcaml_verilator
>= "v0.17.0" -
hardcaml_waveterm
>= "v0.17.0" -
hardcaml_xilinx
>= "v0.17.0" -
hardcaml_xilinx_components
>= "v0.17.0" -
hardcaml_xilinx_reports
>= "v0.17.0" - ppx_hardcaml
Conflicts
None
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