package hardcaml

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package hardcaml
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type !'a write = {
  1. we : 'a;
  2. wd : 'a;
  3. wa : 'a;
}
type !'a read = {
  1. re : 'a;
  2. ra : 'a;
}
type ram = size:int -> we:Types.signal -> wa:Types.signal -> d:Types.signal -> re:Types.signal -> ra:Types.signal -> Types.signal
val ram : ?priority_write:bool -> ram:ram -> size:int -> spec:Types.register -> wr:Types.signal write array -> rd:Types.signal read array -> Types.signal array