package hardcaml

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package hardcaml
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Helper functions to ease usage of the Always API when working with interfaces.

val value : Always.Variable.t t -> Signal.t t

Assign a interface containing variables in an always block.

val reg : ?enable:Signal.t -> Reg_spec.t -> Always.Variable.t t

Creates a interface container with register variables.

Creates a interface container with wire variables, e.g. Foo.Of_always.wire Signal.zero, which would yield wires defaulting to zero.

val match_ : ?default:Always.t Base.list -> Signal.t t -> (Enum.t * Always.t Base.list) Base.list -> Always.t

Performs a "pattern match" on a Signal.t t, and "executes" the branch that matches the signal value. Semantics similar to switch in verilog.

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