package tm-grammars

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package tm-grammars
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Source file tm_grammar_verilog.ml

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let lang_id = "verilog"
let json = {json|{
  "displayName": "Verilog",
  "fileTypes": [
    "v",
    "vh"
  ],
  "name": "verilog",
  "patterns": [
    {
      "include": "#comments"
    },
    {
      "include": "#module_pattern"
    },
    {
      "include": "#keywords"
    },
    {
      "include": "#constants"
    },
    {
      "include": "#strings"
    },
    {
      "include": "#operators"
    }
  ],
  "repository": {
    "comments": {
      "patterns": [
        {
          "begin": "(^[\\t ]+)?(?=//)",
          "beginCaptures": {
            "1": {
              "name": "punctuation.whitespace.comment.leading.verilog"
            }
          },
          "end": "(?!\\G)",
          "patterns": [
            {
              "begin": "//",
              "beginCaptures": {
                "0": {
                  "name": "punctuation.definition.comment.verilog"
                }
              },
              "end": "\\n",
              "name": "comment.line.double-slash.verilog"
            }
          ]
        },
        {
          "begin": "/\\*",
          "end": "\\*/",
          "name": "comment.block.c-style.verilog"
        }
      ]
    },
    "constants": {
      "patterns": [
        {
          "match": "`(?!(celldefine|endcelldefine|default_nettype|define|undef|ifdef|ifndef|else|endif|include|resetall|timescale|unconnected_drive|nounconnected_drive))[A-Z_a-z][$0-9A-Z_a-z]*",
          "name": "variable.other.constant.verilog"
        },
        {
          "match": "[0-9]*'[BDHObdho][XZ_xz\\h]+\\b",
          "name": "constant.numeric.sized_integer.verilog"
        },
        {
          "captures": {
            "1": {
              "name": "constant.numeric.integer.verilog"
            },
            "2": {
              "name": "punctuation.separator.range.verilog"
            },
            "3": {
              "name": "constant.numeric.integer.verilog"
            }
          },
          "match": "\\b(\\d+)(:)(\\d+)\\b",
          "name": "meta.block.numeric.range.verilog"
        },
        {
          "match": "\\b\\d[_\\d]*(?i:e\\d+)?\\b",
          "name": "constant.numeric.integer.verilog"
        },
        {
          "match": "\\b\\d+\\.\\d+(?i:e\\d+)?\\b",
          "name": "constant.numeric.real.verilog"
        },
        {
          "match": "#\\d+",
          "name": "constant.numeric.delay.verilog"
        },
        {
          "match": "\\b[01XZxz]+\\b",
          "name": "constant.numeric.logic.verilog"
        }
      ]
    },
    "instantiation_patterns": {
      "patterns": [
        {
          "include": "#keywords"
        },
        {
          "begin": "^\\s*(?!always|and|assign|output|input|inout|wire|module)([A-Za-z][0-9A-Z_a-z]*)\\s+([A-Za-z][0-9A-Z_a-z]*)(?<!begin|if)\\s*(?=\\(|$)",
          "beginCaptures": {
            "1": {
              "name": "entity.name.tag.module.reference.verilog"
            },
            "2": {
              "name": "entity.name.tag.module.identifier.verilog"
            }
          },
          "end": ";",
          "endCaptures": {
            "0": {
              "name": "punctuation.terminator.expression.verilog"
            }
          },
          "name": "meta.block.instantiation.parameterless.verilog",
          "patterns": [
            {
              "include": "#comments"
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            {
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          "beginCaptures": {
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            }
          },
          "end": ";",
          "endCaptures": {
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              "name": "punctuation.terminator.expression.verilog"
            }
          },
          "name": "meta.block.instantiation.with.parameters.verilog",
          "patterns": [
            {
              "include": "#parenthetical_list"
            },
            {
              "match": "[A-Za-z][0-9A-Z_a-z]*",
              "name": "entity.name.tag.module.identifier.verilog"
            }
          ]
        }
      ]
    },
    "keywords": {
      "patterns": [
        {
          "match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case[xz]?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|output|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor)\\b",
          "name": "keyword.other.verilog"
        },
        {
          "match": "^\\s*`((cell)?define|default_(decay_time|nettype|trireg_strength)|delay_mode_(path|unit|zero)|ifdef|ifndef|include|end(if|celldefine)|else|(no)?unconnected_drive|resetall|timescale|undef)\\b",
          "name": "keyword.other.compiler.directive.verilog"
        },
        {
          "match": "\\$(f(open|close)|readmem([bh])|timeformat|printtimescale|stop|finish|(s|real)?time|realtobits|bitstoreal|rtoi|itor|(f)?(display|write([bh])))\\b",
          "name": "support.function.system.console.tasks.verilog"
        },
        {
          "match": "\\$(random|dist_(chi_square|erlang|exponential|normal|poisson|t|uniform))\\b",
          "name": "support.function.system.random_number.tasks.verilog"
        },
        {
          "match": "\\$((a)?sync\\$((n)?and|(n)or)\\$(array|plane))\\b",
          "name": "support.function.system.pld_modeling.tasks.verilog"
        },
        {
          "match": "\\$(q_(initialize|add|remove|full|exam))\\b",
          "name": "support.function.system.stochastic.tasks.verilog"
        },
        {
          "match": "\\$(hold|nochange|period|recovery|setup(hold)?|skew|width)\\b",
          "name": "support.function.system.timing.tasks.verilog"
        },
        {
          "match": "\\$(dump(file|vars|off|on|all|limit|flush))\\b",
          "name": "support.function.system.vcd.tasks.verilog"
        },
        {
          "match": "\\$(countdrivers|list|input|scope|showscopes|(no)?(key|log)|reset(_(?:count|value))?|(inc)?save|restart|showvars|getpattern|sreadmem([bh])|scale)",
          "name": "support.function.non-standard.tasks.verilog"
        }
      ]
    },
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            },
            "2": {
              "name": "entity.name.type.module.verilog"
            }
          },
          "end": "\\bendmodule\\b",
          "endCaptures": {
            "0": {
              "name": "storage.type.module.verilog"
            }
          },
          "name": "meta.block.module.verilog",
          "patterns": [
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              "include": "#comments"
            },
            {
              "include": "#keywords"
            },
            {
              "include": "#constants"
            },
            {
              "include": "#strings"
            },
            {
              "include": "#instantiation_patterns"
            },
            {
              "include": "#operators"
            }
          ]
        }
      ]
    },
    "operators": {
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          "match": "[-%*+/]|([<>])=?|([!=])?==?|!|&&?|\\|\\|?|\\^?~|~\\^?",
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        }
      ]
    },
    "parenthetical_list": {
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        {
          "begin": "\\(",
          "beginCaptures": {
            "0": {
              "name": "punctuation.section.list.verilog"
            }
          },
          "end": "\\)",
          "endCaptures": {
            "0": {
              "name": "punctuation.section.list.verilog"
            }
          },
          "name": "meta.block.parenthetical_list.verilog",
          "patterns": [
            {
              "include": "#parenthetical_list"
            },
            {
              "include": "#comments"
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    },
    "strings": {
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          "end": "\"",
          "name": "string.quoted.double.verilog",
          "patterns": [
            {
              "match": "\\\\.",
              "name": "constant.character.escape.verilog"
            }
          ]
        }
      ]
    }
  },
  "scopeName": "source.verilog"
}|json}