sail

Sail is a language for describing the instruction semantics of processors
IN THIS PACKAGE
Module Jib_ssa
type 'a array_graph
val make : initial_size:int -> unit -> 'a array_graph
module IntSet : sig ... end
val get_cond : 'a array_graph -> int -> Jib.cval
val get_vertex : 'a array_graph -> int -> ('a * IntSet.t * IntSet.t) option
val iter_graph : ( 'a -> IntSet.t -> IntSet.t -> unit ) -> 'a array_graph -> unit
val add_vertex : 'a -> 'a array_graph -> int
val add_edge : int -> int -> 'a array_graph -> unit
exception Not_a_DAG of int
val topsort : 'a array_graph -> int list
type terminator =
| T_undefined of Jib.ctyp
| T_match_failure
| T_end of Jib.name
| T_goto of string
| T_jump of int * string
| T_label of string
| T_none
type cf_node =
| CF_label of string
| CF_block of Jib.instr list * terminator
| CF_guard of int
| CF_start of Jib.ctyp Jib_util.NameMap.t
val control_flow_graph : Jib.instr list -> int * int list * ('a list * cf_node) array_graph
val immediate_dominators : 'a array_graph -> int -> int array
type ssa_elem =
| Phi of Jib.name * Jib.ctyp * Jib.name list
| Pi of Jib.cval list
val ssa : Jib.instr list -> int * (ssa_elem list * cf_node) array_graph
val make_dot : out_channel -> (ssa_elem list * cf_node) array_graph -> unit
val make_dominators_dot : out_channel -> int array -> (ssa_elem list * cf_node) array_graph -> unit