package rfsm

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  1. VHDL backend
package rfsm
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VHDL backend

module Syntax : SYNTAX
module Static : STATIC
type value
val vhdl_type_of : Syntax.Types.typ -> Vhdl_types.t

vhdl_type_of ty should return the VHDL type corresponding to type ty.

val allowed_shared_type : Syntax.Types.typ -> bool

allowed_shared_type ty should indicate whether type ty can be attributed to a VHDL shared variable.

val pp_type_decl : Stdlib.Format.formatter -> Syntax.type_decl -> unit

pp_type_decl fmt td should print, on formatter fmt, the VHDL translation of type declaration td.

val pp_expr : Stdlib.Format.formatter -> Syntax.expr -> unit

pp_expr fmt e should print, on formatter fmt, the VHDL expression corresponding to expression e.

val pp_lval : Stdlib.Format.formatter -> Syntax.lval -> unit

pp_lval fmt l should print, on formatter fmt, the VHDL representation of l-value l.

val pp_value : Stdlib.Format.formatter -> (value * Vhdl_types.t) -> unit

pp_value fmt (v,t) should print, on formatter fmt, the VHDL value corresponding to value v, with type t.

val pp_type_fns_intf : Stdlib.Format.formatter -> Syntax.type_decl -> unit
val pp_type_fns_impl : Stdlib.Format.formatter -> Syntax.type_decl -> unit

pp_type_fns_intf td (resp. pp_type_fns_impl fmt td) should print, on formatter fmt, the VHDL declaration and implementation (in the entity and architecture definition resp.) corresponding to type declaration td.