package jasmin
Compiler for High-Assurance and High-Speed Cryptography
Install
dune-project
Dependency
Authors
Maintainers
Sources
jasmin-compiler-v2025.06.1.tar.bz2
sha256=e92b42fa69da7c730b0c26dacf842a72b4febcaf4f2157a1dc18b3cce1f859fa
doc/jasmin.jasmin/Jasmin/Arm_instr_decl/index.html
Module Jasmin.Arm_instr_decl
type __ = Obj.t
module E : sig ... end
type arm_options = {
set_flags : bool;
is_conditional : bool;
has_shift : Shift_kind.shift_kind option;
}
val set_flags : arm_options -> bool
val is_conditional : arm_options -> bool
val has_shift : arm_options -> Shift_kind.shift_kind option
type is_arm_options =
| Coq_is_Build_arm_options of bool * Param1.Coq_exports.is_bool * bool * Param1.Coq_exports.is_bool * Shift_kind.shift_kind option * (Shift_kind.shift_kind, Shift_kind.is_shift_kind) Std.Prelude.is_option
val is_arm_options_rect :
(bool ->
Param1.Coq_exports.is_bool ->
bool ->
Param1.Coq_exports.is_bool ->
Shift_kind.shift_kind option ->
(Shift_kind.shift_kind, Shift_kind.is_shift_kind) Std.Prelude.is_option ->
'a1) ->
arm_options ->
is_arm_options ->
'a1
val is_arm_options_rec :
(bool ->
Param1.Coq_exports.is_bool ->
bool ->
Param1.Coq_exports.is_bool ->
Shift_kind.shift_kind option ->
(Shift_kind.shift_kind, Shift_kind.is_shift_kind) Std.Prelude.is_option ->
'a1) ->
arm_options ->
is_arm_options ->
'a1
val arm_options_tag : arm_options -> BinNums.positive
val is_arm_options_inhab : arm_options -> is_arm_options
val is_arm_options_functor : arm_options -> is_arm_options -> is_arm_options
type box_arm_options_Build_arm_options = {
coq_Box_arm_options_Build_arm_options_0 : bool;
coq_Box_arm_options_Build_arm_options_1 : bool;
coq_Box_arm_options_Build_arm_options_2 : Shift_kind.shift_kind option;
}
val coq_Box_arm_options_Build_arm_options_0 :
box_arm_options_Build_arm_options ->
bool
val coq_Box_arm_options_Build_arm_options_1 :
box_arm_options_Build_arm_options ->
bool
val coq_Box_arm_options_Build_arm_options_2 :
box_arm_options_Build_arm_options ->
Shift_kind.shift_kind option
type arm_options_fields_t = box_arm_options_Build_arm_options
val arm_options_fields : arm_options -> arm_options_fields_t
val arm_options_construct :
BinNums.positive ->
box_arm_options_Build_arm_options ->
arm_options option
val arm_options_induction :
(bool ->
Param1.Coq_exports.is_bool ->
bool ->
Param1.Coq_exports.is_bool ->
Shift_kind.shift_kind option ->
(Shift_kind.shift_kind, Shift_kind.is_shift_kind) Std.Prelude.is_option ->
'a1) ->
arm_options ->
is_arm_options ->
'a1
val arm_options_eqb_fields :
(arm_options -> arm_options -> bool) ->
BinNums.positive ->
box_arm_options_Build_arm_options ->
box_arm_options_Build_arm_options ->
bool
val arm_options_eqb : arm_options -> arm_options -> bool
val arm_options_eqb_OK : arm_options -> arm_options -> Bool.reflect
val arm_options_eqb_OK_sumbool : arm_options -> arm_options -> bool
val eqTC_arm_options : arm_options Utils0.eqTypeC
val arm_options_eqType : Eqtype.Equality.coq_type
val default_opts : arm_options
val set_is_conditional : arm_options -> arm_options
val unset_is_conditional : arm_options -> arm_options
val halfword_rect : 'a1 -> 'a1 -> halfword -> 'a1
val halfword_rec : 'a1 -> 'a1 -> halfword -> 'a1
val is_halfword_rect : 'a1 -> 'a1 -> halfword -> is_halfword -> 'a1
val is_halfword_rec : 'a1 -> 'a1 -> halfword -> is_halfword -> 'a1
val halfword_tag : halfword -> BinNums.positive
val is_halfword_inhab : halfword -> is_halfword
val is_halfword_functor : halfword -> is_halfword -> is_halfword
type halfword_fields_t = __
val halfword_fields : halfword -> halfword_fields_t
val halfword_construct :
BinNums.positive ->
halfword_fields_t ->
halfword option
val halfword_induction : 'a1 -> 'a1 -> halfword -> is_halfword -> 'a1
val halfword_eqb_fields :
(halfword -> halfword -> bool) ->
BinNums.positive ->
halfword_fields_t ->
halfword_fields_t ->
bool
val halfword_eqb_OK : halfword -> halfword -> Bool.reflect
type arm_mnemonic =
| ADD
| ADC
| MUL
| MLA
| MLS
| SDIV
| SUB
| SBC
| RSB
| UDIV
| UMULL
| UMAAL
| UMLAL
| SMULL
| SMLAL
| SMMUL
| SMMULR
| SMUL_hw of halfword * halfword
| SMLA_hw of halfword * halfword
| SMULW_hw of halfword
| AND
| BFC
| BFI
| BIC
| EOR
| MVN
| ORR
| ASR
| LSL
| LSR
| ROR
| REV
| REV16
| REVSH
| ADR
| MOV
| MOVT
| UBFX
| UXTB
| UXTH
| SBFX
| CLZ
| CMP
| TST
| CMN
| LDR
| LDRB
| LDRH
| LDRSB
| LDRSH
| STR
| STRB
| STRH
val arm_mnemonic_rect :
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
(halfword -> halfword -> 'a1) ->
(halfword -> halfword -> 'a1) ->
(halfword -> 'a1) ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
arm_mnemonic ->
'a1
val arm_mnemonic_rec :
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
(halfword -> halfword -> 'a1) ->
(halfword -> halfword -> 'a1) ->
(halfword -> 'a1) ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
arm_mnemonic ->
'a1
type is_arm_mnemonic =
| Coq_is_ADD
| Coq_is_ADC
| Coq_is_MUL
| Coq_is_MLA
| Coq_is_MLS
| Coq_is_SDIV
| Coq_is_SUB
| Coq_is_SBC
| Coq_is_RSB
| Coq_is_UDIV
| Coq_is_UMULL
| Coq_is_UMAAL
| Coq_is_UMLAL
| Coq_is_SMULL
| Coq_is_SMLAL
| Coq_is_SMMUL
| Coq_is_SMMULR
| Coq_is_SMUL_hw of halfword * is_halfword * halfword * is_halfword
| Coq_is_SMLA_hw of halfword * is_halfword * halfword * is_halfword
| Coq_is_SMULW_hw of halfword * is_halfword
| Coq_is_AND
| Coq_is_BFC
| Coq_is_BFI
| Coq_is_BIC
| Coq_is_EOR
| Coq_is_MVN
| Coq_is_ORR
| Coq_is_ASR
| Coq_is_LSL
| Coq_is_LSR
| Coq_is_ROR
| Coq_is_REV
| Coq_is_REV16
| Coq_is_REVSH
| Coq_is_ADR
| Coq_is_MOV
| Coq_is_MOVT
| Coq_is_UBFX
| Coq_is_UXTB
| Coq_is_UXTH
| Coq_is_SBFX
| Coq_is_CLZ
| Coq_is_CMP
| Coq_is_TST
| Coq_is_CMN
| Coq_is_LDR
| Coq_is_LDRB
| Coq_is_LDRH
| Coq_is_LDRSB
| Coq_is_LDRSH
| Coq_is_STR
| Coq_is_STRB
| Coq_is_STRH
val is_arm_mnemonic_rect :
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
(halfword -> is_halfword -> halfword -> is_halfword -> 'a1) ->
(halfword -> is_halfword -> halfword -> is_halfword -> 'a1) ->
(halfword -> is_halfword -> 'a1) ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
arm_mnemonic ->
is_arm_mnemonic ->
'a1
val is_arm_mnemonic_rec :
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
(halfword -> is_halfword -> halfword -> is_halfword -> 'a1) ->
(halfword -> is_halfword -> halfword -> is_halfword -> 'a1) ->
(halfword -> is_halfword -> 'a1) ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
arm_mnemonic ->
is_arm_mnemonic ->
'a1
val arm_mnemonic_tag : arm_mnemonic -> BinNums.positive
val is_arm_mnemonic_inhab : arm_mnemonic -> is_arm_mnemonic
val is_arm_mnemonic_functor :
arm_mnemonic ->
is_arm_mnemonic ->
is_arm_mnemonic
val coq_Box_arm_mnemonic_SMUL_hw_0 : box_arm_mnemonic_SMUL_hw -> halfword
val coq_Box_arm_mnemonic_SMUL_hw_1 : box_arm_mnemonic_SMUL_hw -> halfword
type box_arm_mnemonic_SMULW_hw = halfword
val coq_Box_arm_mnemonic_SMULW_hw_0 : box_arm_mnemonic_SMULW_hw -> halfword
type arm_mnemonic_fields_t = __
val arm_mnemonic_fields : arm_mnemonic -> arm_mnemonic_fields_t
val arm_mnemonic_construct :
BinNums.positive ->
arm_mnemonic_fields_t ->
arm_mnemonic option
val arm_mnemonic_induction :
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
(halfword -> is_halfword -> halfword -> is_halfword -> 'a1) ->
(halfword -> is_halfword -> halfword -> is_halfword -> 'a1) ->
(halfword -> is_halfword -> 'a1) ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
'a1 ->
arm_mnemonic ->
is_arm_mnemonic ->
'a1
val arm_mnemonic_eqb_fields :
(arm_mnemonic -> arm_mnemonic -> bool) ->
BinNums.positive ->
arm_mnemonic_fields_t ->
arm_mnemonic_fields_t ->
bool
val arm_mnemonic_eqb : arm_mnemonic -> arm_mnemonic -> bool
val arm_mnemonic_eqb_OK : arm_mnemonic -> arm_mnemonic -> Bool.reflect
val arm_mnemonic_eqb_OK_sumbool : arm_mnemonic -> arm_mnemonic -> bool
val eqTC_arm_mnemonic : arm_mnemonic Utils0.eqTypeC
val arm_mnemonic_eqType : Eqtype.Equality.coq_type
val arm_mnemonics : arm_mnemonic list
val finTC_arm_mnemonic : arm_mnemonic Utils0.finTypeC
val arm_mnemonic_finType : Fintype.Finite.coq_type
val set_flags_mnemonics : arm_mnemonic list
val has_shift_mnemonics : arm_mnemonic list
val condition_mnemonics : arm_mnemonic list
val always_has_shift_mnemonics : (arm_mnemonic * Shift_kind.shift_kind) list
val wsize_uload_mn : (Wsize.wsize * arm_mnemonic) list
val uload_mn_of_wsize : Wsize.wsize -> arm_mnemonic option
val wsize_of_uload_mn : arm_mnemonic -> Wsize.wsize option
val wsize_sload_mn : (Wsize.wsize * arm_mnemonic) list
val sload_mn_of_wsize : Wsize.wsize -> arm_mnemonic option
val wsize_of_sload_mn : arm_mnemonic -> Wsize.wsize option
val wsize_of_load_mn : arm_mnemonic -> Wsize.wsize option
val wsize_store_mn : (Wsize.wsize * arm_mnemonic) list
val store_mn_of_wsize : Wsize.wsize -> arm_mnemonic option
val wsize_of_store_mn : arm_mnemonic -> Wsize.wsize option
val string_of_hw : halfword -> string
val string_of_arm_mnemonic : arm_mnemonic -> string
val arm_op_rect : (arm_mnemonic -> arm_options -> 'a1) -> arm_op -> 'a1
val arm_op_rec : (arm_mnemonic -> arm_options -> 'a1) -> arm_op -> 'a1
val is_arm_op_rect :
(arm_mnemonic -> is_arm_mnemonic -> arm_options -> is_arm_options -> 'a1) ->
arm_op ->
is_arm_op ->
'a1
val is_arm_op_rec :
(arm_mnemonic -> is_arm_mnemonic -> arm_options -> is_arm_options -> 'a1) ->
arm_op ->
is_arm_op ->
'a1
val arm_op_tag : arm_op -> BinNums.positive
type box_arm_op_ARM_op = {
coq_Box_arm_op_ARM_op_0 : arm_mnemonic;
coq_Box_arm_op_ARM_op_1 : arm_options;
}
val coq_Box_arm_op_ARM_op_0 : box_arm_op_ARM_op -> arm_mnemonic
val coq_Box_arm_op_ARM_op_1 : box_arm_op_ARM_op -> arm_options
type arm_op_fields_t = box_arm_op_ARM_op
val arm_op_fields : arm_op -> arm_op_fields_t
val arm_op_construct : BinNums.positive -> box_arm_op_ARM_op -> arm_op option
val arm_op_induction :
(arm_mnemonic -> is_arm_mnemonic -> arm_options -> is_arm_options -> 'a1) ->
arm_op ->
is_arm_op ->
'a1
val arm_op_eqb_fields :
(arm_op -> arm_op -> bool) ->
BinNums.positive ->
box_arm_op_ARM_op ->
box_arm_op_ARM_op ->
bool
val arm_op_eqb_OK : arm_op -> arm_op -> Bool.reflect
val eqTC_arm_op : arm_op Utils0.eqTypeC
val arm_op_eqType : Eqtype.Equality.coq_type
val ad_nz :
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.arg_desc
list
val ad_nzc :
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.arg_desc
list
val ad_nzcv :
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.arg_desc
list
val coq_NF_of_word : Wsize.wsize -> Ssralg.GRing.ComRing.sort -> bool
val coq_ZF_of_word : Wsize.wsize -> Ssralg.GRing.ComRing.sort -> bool
val nzcv_of_aluop :
Wsize.wsize ->
Ssralg.GRing.ComRing.sort ->
BinNums.coq_Z ->
BinNums.coq_Z ->
Sem_type.sem_tuple
val nzcv_w_of_aluop :
Wsize.wsize ->
Ssralg.GRing.ComRing.sort ->
BinNums.coq_Z ->
BinNums.coq_Z ->
Utils0.ltuple
val mk_semi_cond :
Type.stype list ->
Type.stype list ->
Sem_type.sem_tuple Utils0.exec Sem_type.sem_prod ->
Sem_type.sem_tuple Utils0.exec Sem_type.sem_prod
val mk_semi1_shifted :
Shift_kind.shift_kind ->
'a1 Utils0.exec Sem_type.sem_prod ->
'a1 Utils0.exec Sem_type.sem_prod
val mk_semi2_2_shifted :
Type.stype ->
Shift_kind.shift_kind ->
'a1 Utils0.exec Sem_type.sem_prod ->
'a1 Utils0.exec Sem_type.sem_prod
val mk_semi3_2_shifted :
Type.stype ->
Type.stype ->
Shift_kind.shift_kind ->
'a1 Utils0.exec Sem_type.sem_prod ->
'a1 Utils0.exec Sem_type.sem_prod
val mk_shifted :
Shift_kind.shift_kind ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t ->
Sem_type.sem_tuple Utils0.exec Sem_type.sem_prod ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val ak_reg_reg_imm_ :
Arm_expand_imm.expected_wencoding ->
Arch_decl.arg_kind list list list
val ak_reg_reg_imm_shift :
Wsize.wsize ->
Shift_kind.shift_kind ->
Arch_decl.arg_kind list list list
val ak_reg_reg_reg_or_imm_ :
Arm_expand_imm.expected_wencoding ->
Arch_decl.args_kinds list
val ak_reg_reg_reg_or_imm :
arm_options ->
Arm_expand_imm.expected_wencoding ->
Arch_decl.i_args_kinds
val ak_reg_imm_ :
Arm_expand_imm.expected_wencoding ->
Arch_decl.arg_kind list list list
val ak_reg_reg_or_imm_ :
Arm_expand_imm.expected_wencoding ->
Arch_decl.args_kinds list
val ak_reg_reg_or_imm :
arm_options ->
Arm_expand_imm.expected_wencoding ->
Arch_decl.i_args_kinds
val chk_imm_accept_shift : Arm_expand_imm.expected_wencoding
val chk_imm_accept_shift_w12 : arm_options -> Arm_expand_imm.expected_wencoding
val chk_imm_w16_encoding : bool -> Arm_expand_imm.expected_wencoding
val chk_imm_reject_shift : Arm_expand_imm.expected_wencoding
val pp_arm_op :
arm_mnemonic ->
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.asm_arg
list ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.pp_asm_op
val arm_ADD_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_ADD_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_ADC_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
bool ->
Sem_type.sem_tuple
val arm_ADC_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_MUL_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_high_registers : Arm_decl.register list
val arm_MUL_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_MLA_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_MLA_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_MLS_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_MLS_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_SDIV_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_SDIV_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_SUB_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_SUB_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_SBC_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
bool ->
Sem_type.sem_tuple
val arm_SBC_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_RSB_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_UDIV_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_UDIV_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_UMULL_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_UMULL_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_UMAAL_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_UMAAL_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_UMLAL_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_UMLAL_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_SMULL_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_SMULL_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_SMLAL_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_SMLAL_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_SMMUL_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_SMMUL_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_SMMULR_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_SMMULR_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val get_hw :
halfword ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
Ssralg.GRing.ComRing.sort
val arm_smul_hw_semi :
halfword ->
halfword ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg
val arm_smul_hw_instr :
arm_options ->
halfword ->
halfword ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_smla_hw_semi :
halfword ->
halfword ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg
val arm_smla_hw_instr :
arm_options ->
halfword ->
halfword ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_smulw_hw_semi :
halfword ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg
val arm_smulw_hw_instr :
arm_options ->
halfword ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_bitwise_semi :
Wsize.wsize ->
(Ssralg.GRing.ComRing.sort -> Ssralg.GRing.ComRing.sort) ->
(Ssralg.GRing.ComRing.sort -> Ssralg.GRing.ComRing.sort) ->
(Ssralg.GRing.ComRing.sort ->
Ssralg.GRing.ComRing.sort ->
Ssralg.GRing.ComRing.sort) ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_AND_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_BFC_semi_sc : Wsize.safe_cond list
val arm_BFC_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_BFI_semi :
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
Ssralg.GRing.ComRing.sort ->
Ssralg.GRing.ComRing.sort ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg
Utils0.exec
val arm_BFI_semi_sc : Wsize.safe_cond list
val arm_BFI_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_BIC_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_EOR_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_MVN_semi : Sem_type.sem_tuple -> Sem_type.sem_tuple
val arm_MVN_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_ORR_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_shift_semi :
(Sem_type.sem_tuple -> BinNums.coq_Z -> Sem_type.sem_tuple) ->
(Sem_type.sem_tuple -> BinNums.coq_Z -> bool) ->
Sem_type.sem_tuple ->
Ssralg.GRing.ComRing.sort ->
Sem_type.sem_tuple
val arm_ASR_C : Sem_type.sem_tuple -> BinNums.coq_Z -> bool
val arm_ASR_semi :
Sem_type.sem_tuple ->
Ssralg.GRing.ComRing.sort ->
Sem_type.sem_tuple
val arm_ASR_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_LSL_C : Sem_type.sem_tuple -> BinNums.coq_Z -> bool
val arm_LSL_semi :
Sem_type.sem_tuple ->
Ssralg.GRing.ComRing.sort ->
Sem_type.sem_tuple
val arm_LSL_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_LSR_C : Sem_type.sem_tuple -> BinNums.coq_Z -> bool
val arm_LSR_semi :
Sem_type.sem_tuple ->
Ssralg.GRing.ComRing.sort ->
Sem_type.sem_tuple
val arm_LSR_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_ROR_C : Sem_type.sem_tuple -> BinNums.coq_Z -> bool
val arm_ROR_semi :
Sem_type.sem_tuple ->
Ssralg.GRing.ComRing.sort ->
Sem_type.sem_tuple
val arm_ROR_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val mk_rev_instr :
arm_options ->
arm_mnemonic ->
Sem_type.sem_tuple Sem_type.sem_prod ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_REV_semi : Sem_type.sem_tuple -> Sem_type.sem_tuple
val arm_REV16_semi : Sem_type.sem_tuple -> Sem_type.sem_tuple
val arm_REVSH_semi : Sem_type.sem_tuple -> Sem_type.sem_tuple
val arm_REV_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_REV16_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_REVSH_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_ADR_semi : Sem_type.sem_tuple -> Sem_type.sem_tuple
val arm_ADR_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_MOV_semi : Sem_type.sem_tuple -> Sem_type.sem_tuple
val arm_MOV_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_MOVT_semi :
Sem_type.sem_tuple ->
Ssralg.GRing.ComRing.sort ->
Sem_type.sem_tuple
val arm_MOVT_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val bit_field_extract_semi :
((Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
BinNums.coq_Z ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg) ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
Ssralg.GRing.ComRing.sort ->
Ssralg.GRing.ComRing.sort ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg
Utils0.exec
val bit_field_extract_semi_sc : Wsize.safe_cond list
val ak_reg_reg_imm_imm_extr : Arch_decl.arg_kind list list list
val arm_UBFX_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val extend_bits_semi :
BinNums.coq_Z ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg ->
Ssralg.GRing.ComRing.sort ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.wreg
val ak_reg_reg_imm8_0_8_16_24 : Arch_decl.arg_kind list list list
val arm_UXTB_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_UXTH_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_SBFX_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_CMP_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_CMP_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_TST_semi :
Sem_type.sem_tuple ->
Sem_type.sem_tuple ->
Sem_type.sem_tuple
val arm_TST_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_CMN_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_extend_semi :
Wsize.wsize ->
bool ->
Wsize.wsize ->
Ssralg.GRing.ComRing.sort ->
Ssralg.GRing.ComRing.sort
val arm_load_instr :
arm_options ->
arm_mnemonic ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_store_instr :
arm_options ->
arm_mnemonic ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_CLZ_instr :
arm_options ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val mn_desc :
arm_options ->
arm_mnemonic ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_instr_desc :
arm_op ->
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt)
Arch_decl.instr_desc_t
val arm_prim_string : (string * arm_op Sopn.prim_constructor) list
val arm_op_decl :
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt,
arm_op)
Arch_decl.asm_op_decl
type arm_prog =
(Arm_decl.register,
Arch_utils.empty,
Arch_utils.empty,
Arm_decl.rflag,
Arm_decl.condt,
arm_op)
Arch_decl.asm_prog
sectionYPositions = computeSectionYPositions($el), 10)"
x-init="setTimeout(() => sectionYPositions = computeSectionYPositions($el), 10)"
>