package hardcaml_xilinx

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package hardcaml_xilinx
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Source file hardcaml_xilinx__.ml

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(* generated by dune *)

(** @canonical Hardcaml_xilinx.Byte_write_width *)
module Byte_write_width = Hardcaml_xilinx__Byte_write_width

(** @canonical Hardcaml_xilinx.Cascade_height *)
module Cascade_height = Hardcaml_xilinx__Cascade_height

(** @canonical Hardcaml_xilinx.Collision_mode *)
module Collision_mode = Hardcaml_xilinx__Collision_mode

(** @canonical Hardcaml_xilinx.Dual_port_ram *)
module Dual_port_ram = Hardcaml_xilinx__Dual_port_ram

(** @canonical Hardcaml_xilinx.Fifo_async *)
module Fifo_async = Hardcaml_xilinx__Fifo_async

(** @canonical Hardcaml_xilinx.Fifo_memory_type *)
module Fifo_memory_type = Hardcaml_xilinx__Fifo_memory_type

(** @canonical Hardcaml_xilinx.Fifo_sync *)
module Fifo_sync = Hardcaml_xilinx__Fifo_sync

(** @canonical Hardcaml_xilinx.Icape3 *)
module Icape3 = Hardcaml_xilinx__Icape3

(** @canonical Hardcaml_xilinx.Memory_builder *)
module Memory_builder = Hardcaml_xilinx__Memory_builder

(** @canonical Hardcaml_xilinx.Ram_arch *)
module Ram_arch = Hardcaml_xilinx__Ram_arch

(** @canonical Hardcaml_xilinx.Ram_port *)
module Ram_port = Hardcaml_xilinx__Ram_port

(** @canonical Hardcaml_xilinx.Ram_port_with_clear *)
module Ram_port_with_clear = Hardcaml_xilinx__Ram_port_with_clear

(** @canonical Hardcaml_xilinx.Ram_with_resizing *)
module Ram_with_resizing = Hardcaml_xilinx__Ram_with_resizing

(** @canonical Hardcaml_xilinx.Ram_with_resizing_intf *)
module Ram_with_resizing_intf = Hardcaml_xilinx__Ram_with_resizing_intf

(** @canonical Hardcaml_xilinx.Simple_dual_port_ram *)
module Simple_dual_port_ram = Hardcaml_xilinx__Simple_dual_port_ram

(** @canonical Hardcaml_xilinx.Synthesis *)
module Synthesis = Hardcaml_xilinx__Synthesis

(** @canonical Hardcaml_xilinx.Synthesis_intf *)
module Synthesis_intf = Hardcaml_xilinx__Synthesis_intf

(** @canonical Hardcaml_xilinx.True_dual_port_ram *)
module True_dual_port_ram = Hardcaml_xilinx__True_dual_port_ram

(** @canonical Hardcaml_xilinx.Unisim_2019_1 *)
module Unisim_2019_1 = Hardcaml_xilinx__Unisim_2019_1

(** @canonical Hardcaml_xilinx.Xpm_2019_1 *)
module Xpm_2019_1 = Hardcaml_xilinx__Xpm_2019_1

(** @canonical Hardcaml_xilinx.Xpm_2022_1 *)
module Xpm_2022_1 = Hardcaml_xilinx__Xpm_2022_1

(** @canonical Hardcaml_xilinx.Xpm_fifo_async *)
module Xpm_fifo_async = Hardcaml_xilinx__Xpm_fifo_async

(** @canonical Hardcaml_xilinx.Xpm_fifo_sync *)
module Xpm_fifo_sync = Hardcaml_xilinx__Xpm_fifo_sync