A Display_rules.t is an ordered list of rules that specifies the order of ports and the formatting of signals in a waveform.
A port is displayed according to the first rule that it matches, using that rule's wave format. Ports matching rules earlier in the list are displayed above ports matching rules later in the list.
type t = Display_rule.t Base.listval sexp_of_t : t -> Sexplib0.Sexp.tval run_rule :
Display_rule.t ->
Hardcaml_waveterm_kernel__.Port.t ->
(Wave_format.t * Text_alignment.t) Base.optionval sort_ports_and_formats :
t ->
Hardcaml_waveterm_kernel__.Port.t Base.list ->
(Hardcaml_waveterm_kernel__.Port.t
* (Wave_format.t * Text_alignment.t) Base.option)
Base.listConstruct the port order and formatting from the display rules and ports (derived from a testbench simulation object). Unmatched ports are not shown, unless Rule.default (or a similar custom rule) is included as the last display rule.
Check if a given port is displayed by any of the rules.
val is_signal_displayed : t -> Hardcaml.Signal.t -> Base.boolCheck if a given signal (treated as an internal port) is displayed by any of the rules.
module With_interface (I : Hardcaml.Interface.S) : sig ... endCreate rules for each signal in the interface.