package hardcaml_waveterm

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package hardcaml_waveterm
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Module Hardcaml_waveterm.Port

Simulation port description.

module Type : sig ... end
type t = {
  1. type_ : Type.t;
  2. port_name : Port_name.t;
  3. width : Import.int;
}
val compare : t -> t -> Import.int
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t