package hardcaml_verilator

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in-package search v0.2.0

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Parameters
Signature

hardcaml_verilator
- Hardcaml_verilator
  - Cache
  - Simulation_backend
  - With_interface
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name

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Module
Module type
Parameter
Class
Class type

Parameters

module I : Hardcaml.Interface.S

module O : Hardcaml.Interface.S

Signature

val create : 
  (clock_names:string list ->
    (Hardcaml.Signal.t I.t -> Hardcaml.Signal.t O.t) ->
    (Hardcaml.Bits.t Stdlib.ref I.t, Hardcaml.Bits.t Stdlib.ref O.t)
      Hardcaml.Cyclesim.t)
    with_options

val create_shared_object : 
  ((Hardcaml.Signal.t I.t -> Hardcaml.Signal.t O.t) -> string) with_options

Compiles a circuit and returns the shared object which can later be passed as the file_name with Cache.Explicit to the cache input.