package hardcaml_verify

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in-package search v0.2.0

hardcaml_verify
- Hardcaml_verify
  - Nusmv
    
    Counter_example_trace
hardcaml_verify.kernel
- Hardcaml_verify_kernel
  - Basic_gates
    
    Uid
  - Cnf
    
    Conjunction
    
    Disjunction
    
    Literal
    
    Model
    
    Model_with_bits
    
    Model_with_vectors
  - Comb_gates
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
  - Dimacs
  - Is_one_hot
    
    Make
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
  - Label
    
    Uid
  - Nusmv
    
    Circuit_properties
    
    Counter_example_trace
    
    Output_parser
    
    Proof_result
    
    With_interface
    
    I
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Sat
  - Sec
    
    Equivalence_result
    
    Instantiation_ports_match
    
    Proposition
  - Solver
  - Tseitin
    
    Make
    
    B
    
    S

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module Basic_gates : sig ... end

module Cnf : sig ... end

Data structure for creating CNF formulae.

module Comb_gates : sig ... end

Hardcaml combinational logic API using lists of Basic_gate.ts.

module Dimacs : sig ... end

module Is_one_hot : sig ... end

Computes information about the one-hotness of a vector. In addition it can compute if no bits are set or more than 1 bit is set.

module Label : sig ... end

Labels represent named variables. They contain a uid (unique identifier) which is constructed when the label is created. The name is not used for comparison.

module Nusmv : sig ... end

module Sat : sig ... end

module Sec : sig ... end

Sequential equivalence checking.

module Solver : sig ... end

module Tseitin : sig ... end