package hardcaml_fixed_point
Library
Module
Module type
Parameter
Class
Class type
val sexp_of_t : t -> Sexplib0.Sexp.t
include Base.Equal.S with type t := t
val equal : t Base__Equal.equal
val empty : t
the empty signal
val is_empty : t -> Base.bool
names a signal
let a = a -- "a" in ...
signals may have multiple names.
val width : t -> Base.int
returns the width (number of bits) of a signal.
let w = width s in ...
addess_bits_for num_elements
returns the address width required to index num_elements
.
It is the same as Int.ceil_log2
, except it wll return a minimum value of 1 (since you cannot have 0 width vectors). Raises if num_elements
is < 0
.
num_bits_to_represent x
returns the number of bits required to represent the number x
, which should be >= 0
.
val of_constant : Hardcaml.Constant.t -> t
val to_constant : t -> Hardcaml.Constant.t
val of_bit_string : Base.string -> t
convert binary string to constant
val of_int : width:Base.int -> Base.int -> t
convert integer to constant
val of_int32 : width:Base.int -> Base.int32 -> t
val of_int64 : width:Base.int -> Base.int64 -> t
val of_hex :
?signedness:Hardcaml.Constant.Signedness.t ->
width:Base.int ->
Base.string ->
t
convert hex string to a constant. If the target width is greater than the hex length and signedness
is Signed
then the result is sign extended. Otherwise the result is zero padded.
val of_octal :
?signedness:Hardcaml.Constant.Signedness.t ->
width:Base.int ->
Base.string ->
t
convert octal string to a constant. If the target width is greater than the octal length and signedness
is Signed
then the result is sign extended. Otherwise the result is zero padded.
val of_string : Base.string -> t
convert verilog style or binary string to constant
val of_bit_list : Base.int Base.list -> t
convert IntbitsList to constant
val of_decimal_string : width:Base.int -> Base.string -> t
val of_char : Base.char -> t
convert a char
to an 8 bit constant
val of_bool : Base.bool -> t
convert a bool
to vdd
or gnd
val to_z : t -> signedness:Hardcaml.Constant.Signedness.t -> Z.t
Convert bits to a Zarith.t
concat ts
concatenates a list of signals - the msb of the head of the list will become the msb of the result.
let c = concat [ a; b; c ] in ...
concat
raises if ts
is empty or if any t
in ts
is empty.
Similar to concat_msb
except the lsb of the head of the list will become the lsb of the result.
val vdd : t
logic 1
val is_vdd : t -> Base.bool
val gnd : t
logic 0
val is_gnd : t -> Base.bool
val zero : Base.int -> t
zero w
makes a the zero valued constant of width w
val ones : Base.int -> t
ones w
makes a constant of all ones of width w
val one : Base.int -> t
one w
makes a one valued constant of width w
select t hi lo
selects from t
bits in the range hi
...lo
, inclusive. select
raises unless hi
and lo
fall within 0 .. width t - 1
and hi >=
lo
.
x.:+[lo, width]
== select x (lo + width - 1) lo
. If width
is None
it selects all remaining msbs of the vector ie x.:+[lo,None]
== drop_bottom x lo
x.:-[hi, width]
== select x hi (hi - width + 1)
. If hi
is None
it defaults to the msb of the vector ie x.:-[None, width]
== sel_top x width
insert ~into:t x ~at_offset
insert x
into t
at given offet
multiplexer.
let m = mux sel inputs in ...
Given l
= List.length inputs
and w
= width sel
the following conditions must hold.
l
<= 2**w
, l
>= 2
If l
< 2**w
, the last input is repeated.
All inputs provided must have the same width, which will in turn be equal to the width of m
.
mux2 c t f
2 input multiplexer. Selects t
if c
is high otherwise f
.
t
and f
must have same width and c
must be 1 bit.
Equivalent to mux c [f; t]
val to_string : t -> Base.string
create string from signal
val to_int : t -> Base.int
to_int t
treats t
as unsigned and resizes it to fit exactly within an OCaml Int.t
.
- If
width t > Int.num_bits
then the upper bits are truncated. - If
width t >= Int.num_bits
andbit t (Int.num_bits-1) = vdd
(i.e. the msb of the resultingInt.t
is set), then the result is negative. - If
t
isSignal.t
and not a constant value, an exception is raised.
val to_sint : t -> Base.int
to_sint t
treats t
as signed and resizes it to fit exactly within an OCaml Int.t
.
- If
width t > Int.num_bits
then the upper bits are truncated. - If
t
isSignal.t
and not a constant value, an exception is raised.
val to_int32 : t -> Base.int32
val to_sint32 : t -> Base.int32
val to_int64 : t -> Base.int64
val to_sint64 : t -> Base.int64
val to_bool : t -> Base.bool
val to_char : t -> Base.char
Convert signal to a char
. The signal must be 8 bits wide.
val to_bstr : t -> Base.string
create binary string from signal
split signal in half. The most significant bits will be in the left half of the returned tuple.
Split signal into a list of signals with width equal to part_width
. The least significant bits are at the head of the returned list. If exact
is true
the input signal width must be exactly divisable by part_width
. When exact
is false
and the input signal width is not exactly divisible by part_width
, the last element will contains residual bits.
eg:
split_lsb ~part_width:4 16b0001_0010_0011_0100 = [ 4b0100; 4b0011; 4b0010; 4b0001 ] split_lsb ~exact:false ~part_width:4 17b11_0001_0010_0011_0100 = [ 4b0100; 4b0011; 4b0010; 4b0001; 2b11 ]
Like split_lsb
except the most significant bits are at the head of the returned list. Residual bits when exact
is false
goes to the last element of the list, so in the general case split_lsb
is not necessarily equivalent to split_msb |> List.rev
.
uresize t w
returns the unsigned resize of t
to width w
. If w = width t
, this is a no-op. If w < width t
, this select
s the w
low bits of t
. If w >
width t
, this extends t
with zero (w - width t)
.
sresize t w
returns the signed resize of t
to width w
. If w = width t
, this is a no-op. If w < width t
, this select
s the w
low bits of t
. If w >
width t
, this extends t
with w - width t
copies of msb t
.
resize_list ?resize l
finds the maximum width in l
and applies resize el max
to each element.
resize_op2 ~resize f a b
applies resize x w
to a
and b
where w
is the maximum of their widths. It then returns f a b
mod_counter max t
is if t = max then 0 else (t + 1)
, and can be used to count from 0 to max
then from zero again. If max == (1<<n - 1)
, then a comparator is not generated and overflow arithmetic is used instead.
compute_arity ~steps num_values
computes the tree arity required to reduce num_values
in steps
. steps<=0
raises.
compute_tree_branches ~steps num_values
returns a list of length steps
of branching factors required to reduce num_values
. This tends to produce a slightly more balanced sequence than just applying compute_arity
at every step.
tree ~arity ~f input
creates a tree of operations. The arity of the operator is configurable. tree
raises if input = []
.
val priority_select :
?branching_factor:Base.int ->
(t, t) Hardcaml__.Comb_intf.with_valid2 Base.list ->
(t, t) Hardcaml__.Comb_intf.with_valid2
priority_select cases
returns the value associated with the first case whose valid
signal is high. valid
will be set low in the returned with_valid
if no case is selected.
val priority_select_with_default :
?branching_factor:Base.int ->
(t, t) Hardcaml__.Comb_intf.with_valid2 Base.list ->
default:t ->
t
Same as priority_select
except returns default
if no case matches.
val onehot_select :
?branching_factor:Base.int ->
(t, t) Hardcaml__.Comb_intf.with_valid2 Base.list ->
t
Select a case where one and only one valid
signal is enabled. If more than one case is valid
then the return value is undefined. If no cases are valid, 0
is returned by the current implementation, though this should not be relied upon.
is_pow2 t
returns a bit to indicate if t
is a power of 2.
leading_ones t
returns the number of consecutive 1
s from the most significant bit of t
down.
trailing_ones t
returns the number of consecutive 1
s from the least significant bit of t
up.
leading_zeros t
returns the number of consecutive 0
s from the most significant bit of t
down.
trailing_zeros t
returns the number of consecutive 0
s from the least significant bit of t
up.
floor_log2 x
returns the floor of log-base-2 of x
. x
is treated as unsigned and an error is indicated by valid = gnd
in the return value if x = 0
.
ceil_log2 x
returns the ceiling of log-base-2 of x
. x
is treated as unsigned and an error is indicated by valid = gnd
in the return value if x = 0
.
val random : width:Base.int -> t
create random constant vector of given width
module type TypedMath = sig ... end