package hardcaml_event_driven_sim

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package hardcaml_event_driven_sim

hardcaml_event_driven_sim
- CHANGES
- LICENSE
- Library hardcaml_event_driven_sim
  - Hardcaml_event_driven_sim
    
    Config
    
    Logic
    
    S
    
    Typed_math
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Four_state_logic
    
    Typed_math
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Two_state_logic
    
    Typed_math
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Vcd
    
    Make
    
    Ops
    
    S
    
    Make
    
    Port
    
    Waveterm
    
    Sim
    
    Events
    
    Wave
    
    Waves
    
    Config
    
    Render
    
    Styles
    
    Bounds
    
    Make
    
    Static
    
    R
    
    Waveform
    
    Serialize
    
    Expect
    
    Make
    
    With_interface
    
    Make
    
    Config
    
    Event_simulator
    
    Logic
    
    Ops
    
    Vcd
    
    With_interface
    
    Input
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Output
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Logic
    
    Typed_math
    
    Unsigned
    
    Signed
    
    Uop
    
    Sop
    
    Ops
- Library hardcaml_event_driven_sim.kernel
  - Event_driven_sim
    
    Mini_async
    
    Deferred
    
    Monad_infix
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Let_syntax
    
    Ivar
    
    Simulator
    
    Value_S
    
    Signal_id
    
    Signal
    
    Process
    
    Expert
    
    Async
    
    Let_syntax
    
    Deferred
    
    Ivar
    
    Change_monitor
    
    Debug
    
    Version_signal
- Sources
  - hardcaml_event_driven_sim
    
    four_state_logic.ml
    
    hardcaml_event_driven_sim.ml
    
    hardcaml_event_driven_sim__.ml
    
    logic.ml
    
    logic_intf.ml
    
    ops.ml
    
    ops_intf.ml
    
    port.ml
    
    two_state_logic.ml
    
    vcd.ml
    
    waveterm.ml
    
    with_interface.ml
    
    with_interface_intf.ml
  - hardcaml_event_driven_sim.kernel
    
    event_driven_sim.ml
    
    mini_async.ml
    
    simulator.ml

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Module `Simulator.Process`Source

Sourcetype t

Sourceval create : Signal_id.t list -> (unit -> unit) -> t