package hardcaml_axi

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package hardcaml_axi
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When placed between two components which produce/consume an AXI stream, this module ensures that every output signal is registerd. It fully supports the tvalid/tready handshake protocol.

module IO : sig ... end
module I : sig ... end
module Pipeline_stage_descr : sig ... end
val pipeline_expert : pipeline_stages:Pipeline_stage_descr.t Base.list -> scope:Hardcaml.Scope.t -> clock:Hardcaml.Signal.t -> io:Hardcaml.Signal.t IO.t -> Hardcaml.Signal.t IO.t

Instantiates a chain of n Datapath_register components and wire up the source and dest signals appropriately.

In most cases, you probably want to use pipeline_simple.

val pipeline_simple : ?instance_name:Base.string -> n:Base.int -> Hardcaml.Scope.t -> Hardcaml.Signal.t I.t -> Hardcaml.Signal.t IO.t

Construacts a datapath register pipeline with n stages, where all the pipeline stages have the same clear and same instance name.

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