package hardcaml

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package hardcaml
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Module Hardcaml.Write_portSource

A memory write port.

Sourcetype 'a t = {
  1. write_clock : 'a;
  2. write_address : 'a;
  3. write_enable : 'a;
  4. write_data : 'a;
}
Sourceval sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t

A partial Interface implementation

Use with Interface.Update to create a full interface specification.

Sourceval iter : 'a t -> f:('a -> Base.unit) -> Base.unit
Sourceval iter2 : 'a t -> 'b t -> f:('a -> 'b -> Base.unit) -> Base.unit
Sourceval map : 'a t -> f:('a -> 'b) -> 'b t
Sourceval map2 : 'a t -> 'b t -> f:('a -> 'b -> 'c) -> 'c t
Sourceval to_list : 'a t -> 'a Base.list
Sourceval port_names : Base.string t