package hardcaml

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Parameters
Signature

package hardcaml

hardcaml
- HardCaml
  - Bits
    
    ArraybitsBase
    
    ArraybitsBuilder
    
    B
    
    Comb
    
    ArraybitsInt32
    
    Signed
    
    TypedMath
    
    Unsigned
    
    ArraybitsInt64
    
    Signed
    
    TypedMath
    
    Unsigned
    
    ArraybitsNativeint
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Int32bits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Int64bits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Intbits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    IntbitsList
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Nativeintbits
    
    Signed
    
    TypedMath
    
    Unsigned
  - Bits_raw
    
    RawBuilder
    
    B
  - C
  - Circuit
    
    Hierarchy
    
    Mangler
  - Comb
    
    Make
    
    Bits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    S
    
    Signed
    
    TypedMath
    
    Unsigned
    
    T
  - Const_prop
    
    Base
    
    Comb
    
    Signed
    
    TypedMath
    
    Unsigned
  - Cyclesim
    
    Api
    
    Make
    
    Bits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    InstOps
    
    Real
    
    Double
    
    Float
    
    P
    
    Real
  - Fixed
    
    Make
    
    B
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Fixed
    
    Overflow
    
    Round
    
    Signed
    
    Make
    
    S
    
    Overflow
    
    Round
    
    Spec
    
    Unsigned
    
    Make
    
    S
    
    Overflow
    
    Round
    
    Spec
  - Interface
    
    Circ
    
    I
    
    O
    
    Empty
    
    Gen
    
    B
    
    Signed
    
    TypedMath
    
    Unsigned
    
    I
    
    O
    
    Hier
    
    I
    
    O
    
    Inst
    
    I
    
    O
    
    S
    
    Sim
    
    B
    
    Signed
    
    TypedMath
    
    Unsigned
    
    I
    
    O
  - Rtl
    
    Hierarchy
    
    Rtl_S
    
    Verilog
    
    Vhdl
  - Signal
    
    Base
    
    Comb
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Guarded
    
    variable
    
    Instantiation
    
    Seq
    
    Types
    
    UidMap
    
    UidSet
  - Structural
    
    Base
    
    C
    
    Base0
    
    Base1
    
    Base2
    
    Config
  - Structural_lib
  - Syntax
  - Transform
    
    AigTransform
    
    ConstantPropagation
    
    CopyTransform
    
    MakeAig
    
    B
    
    MakeCombTransform
    
    B
    
    MakeNand
    
    B
    
    MakeNor
    
    B
    
    NandTransform
    
    NorTransform
    
    Signals
    
    Aig
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Nand
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Nor
    
    Signed
    
    TypedMath
    
    Unsigned
    
    SimplifyBusses
    
    SimplifyConstants
    
    TransformFn
  - Utils
  - Vcd
    
    Make
    
    S
    
    Signed
    
    TypedMath
    
    Unsigned
  - Vcd_ext
    
    Make
    
    S
    
    Signed
    
    TypedMath
    
    Unsigned
  - Xilinx
    
    HardCaml_api
    
    Lut4
    
    Lut6
    
    LutEqn
    
    LutSize
    
    S
    
    T
    
    Unisim
    
    XComb
    
    Synth
    
    XMake
    
    L
    
    X
    
    XSynthesize
    
    L
    
    X
    
    XSynthesizeComb
    
    L
    
    X
hardcaml.js
- HardCaml
  - Bits
    
    ArraybitsBase
    
    ArraybitsBuilder
    
    B
    
    Comb
    
    ArraybitsInt32
    
    Signed
    
    TypedMath
    
    Unsigned
    
    ArraybitsInt64
    
    Signed
    
    TypedMath
    
    Unsigned
    
    ArraybitsNativeint
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Int32bits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Int64bits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Intbits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    IntbitsList
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Nativeintbits
    
    Signed
    
    TypedMath
    
    Unsigned
  - Bits_raw
    
    RawBuilder
    
    B
  - C
  - Circuit
    
    Hierarchy
    
    Mangler
  - Comb
    
    Make
    
    Bits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    S
    
    Signed
    
    TypedMath
    
    Unsigned
    
    T
  - Const_prop
    
    Base
    
    Comb
    
    Signed
    
    TypedMath
    
    Unsigned
  - Cyclesim
    
    Api
    
    Make
    
    Bits
    
    Signed
    
    TypedMath
    
    Unsigned
    
    InstOps
    
    Real
    
    Double
    
    Float
    
    P
    
    Real
  - Fixed
    
    Make
    
    B
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Fixed
    
    Overflow
    
    Round
    
    Signed
    
    Make
    
    S
    
    Overflow
    
    Round
    
    Spec
    
    Unsigned
    
    Make
    
    S
    
    Overflow
    
    Round
    
    Spec
  - Interface
    
    Circ
    
    I
    
    O
    
    Empty
    
    Gen
    
    B
    
    Signed
    
    TypedMath
    
    Unsigned
    
    I
    
    O
    
    Hier
    
    I
    
    O
    
    Inst
    
    I
    
    O
    
    S
    
    Sim
    
    B
    
    Signed
    
    TypedMath
    
    Unsigned
    
    I
    
    O
  - Rtl
    
    Hierarchy
    
    Rtl_S
    
    Verilog
    
    Vhdl
  - Signal
    
    Base
    
    Comb
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Guarded
    
    variable
    
    Instantiation
    
    Seq
    
    Types
    
    UidMap
    
    UidSet
  - Structural
    
    Base
    
    C
    
    Base0
    
    Base1
    
    Base2
    
    Config
  - Structural_lib
  - Syntax
  - Transform
    
    AigTransform
    
    ConstantPropagation
    
    CopyTransform
    
    MakeAig
    
    B
    
    MakeCombTransform
    
    B
    
    MakeNand
    
    B
    
    MakeNor
    
    B
    
    NandTransform
    
    NorTransform
    
    Signals
    
    Aig
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Nand
    
    Signed
    
    TypedMath
    
    Unsigned
    
    Nor
    
    Signed
    
    TypedMath
    
    Unsigned
    
    SimplifyBusses
    
    SimplifyConstants
    
    TransformFn
  - Utils
  - Vcd
    
    Make
    
    S
    
    Signed
    
    TypedMath
    
    Unsigned
  - Vcd_ext
    
    Make
    
    S
    
    Signed
    
    TypedMath
    
    Unsigned
  - Xilinx
    
    HardCaml_api
    
    Lut4
    
    Lut6
    
    LutEqn
    
    LutSize
    
    S
    
    T
    
    Unisim
    
    XComb
    
    Synth
    
    XMake
    
    L
    
    X
    
    XSynthesize
    
    L
    
    X
    
    XSynthesizeComb
    
    L
    
    X
- HardCamlJS
  - Wave
    
    Gui

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Module
Module type
Parameter
Class
Class type

Parameters

module I : S

module O : S

Signature

val make : 
  Circuit.Hierarchy.database ->
  string ->
  (Signal.Comb.t I.t -> Signal.Comb.t O.t) ->
  Signal.Comb.t I.t ->
  Signal.Comb.t O.t