package hardcaml-llvmsim

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Class type
type global_type =
  1. | G_Port
  2. | G_Internal
  3. | G_Reg
  4. | G_Mem
type global = {
  1. width : int;
  2. rnd_width : int;
  3. cur : Llvm.llvalue;
  4. next : Llvm.llvalue;
  5. typ : global_type;
}
type global_simple = bool -> int -> HardCaml.Signal.Types.signal -> global
type global_reg = int -> HardCaml.Signal.Types.signal -> global
type global_mem = int -> int -> HardCaml.Signal.Types.signal -> global
type load_simple = bool -> HardCaml.Signal.Types.signal -> Llvm.llvalue
type load_reg = HardCaml.Signal.Types.signal -> Llvm.llvalue
type load_mem = Llvm.llvalue -> HardCaml.Signal.Types.signal -> Llvm.llvalue
type store_simple = Llvm.llvalue -> bool -> HardCaml.Signal.Types.signal -> unit
type store_reg = Llvm.llvalue -> HardCaml.Signal.Types.signal -> unit
type store_mem = Llvm.llvalue -> HardCaml.Signal.Types.signal -> unit
type update_reg = HardCaml.Signal.Types.signal -> unit
type update_mem = Llvm.llvalue -> HardCaml.Signal.Types.signal -> unit
type globals = {
  1. gmap : global HardCaml.Signal.Types.UidMap.t Stdlib.ref;
  2. gsimple : global_simple;
  3. greg : global_reg;
  4. gmem : global_mem;
  5. fscope : Llvm.llvalue Utils.func -> func;
}
and func = {
  1. loads : loads;
  2. stores : stores;
  3. updates : updates;
}
and loads = {
  1. lsimple : load_simple;
  2. lreg : load_reg;
  3. lmem : load_mem;
}
and stores = {
  1. ssimple : store_simple;
  2. sreg : store_reg;
  3. smem : store_mem;
}
and updates = {
  1. ureg : update_reg;
  2. umem : update_mem;
}
val global_fns : Llvm.llmodule -> globals
val load_signal : ?rd_mem:bool -> func -> Llvm.llvalue HardCaml.Signal.Types.UidMap.t -> HardCaml.Signal.Types.signal -> Llvm.llvalue HardCaml.Signal.Types.UidMap.t * Llvm.llvalue
val store_signal : func -> Llvm.llvalue -> HardCaml.Signal.Types.signal -> unit
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