package cpuid

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package cpuid
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Detect CPU features.

v0.1.2 — homepage

Overview

Cpuid provides runtime detection of CPU features through the x86 CPUID instruction. Detection discovers the CPU vendor and a set of feature flags.

The flag names reflect the Linux convention, except in uppercase. Only the features reported by the CPU are included (i.e. there are no synthetic flags).

Limitations

Cpuid currently relies on an x86-specific feature. The library runs on ARM processors, but calls return an error.

The only CPUID-leaves consulted for feature flags are 0x1, 0x7:0 and 0x80000001. Hence, the reported features are a subset of what Linux would report.

Number of cores is CPUID 0xb:1 EBX. This only works on Intel CPUs after around 2010, and fails under virtualization.

Cpuid

type error = [
  1. | `Unsupported
]
type nonrec 'a result = ('a, error) result
type vendor = [
  1. | `AMD
  2. | `Centaur
  3. | `Cyrix
  4. | `Intel
  5. | `Transmeta
  6. | `NSC
  7. | `NexGen
  8. | `Rise
  9. | `SiS
  10. | `UMC
  11. | `VIA
  12. | `Vortex
  13. | `KVM
  14. | `Hyper_V
  15. | `Parallels
  16. | `VMware
  17. | `Xen
  18. | `UNKNOWN
]

The CPU manufacturer, the type of virtual environment, or `UNKNOWN.

type flag = [
  1. | `FPU
    (*

    Onboard FPU

    *)
  2. | `VME
    (*

    Virtual Mode Extensions

    *)
  3. | `DE
    (*

    Debugging Extensions

    *)
  4. | `PSE
    (*

    Page Size Extensions

    *)
  5. | `TSC
    (*

    Time Stamp Counter

    *)
  6. | `MSR
    (*

    Model-Specific Registers

    *)
  7. | `PAE
    (*

    Physical Address Extensions

    *)
  8. | `MCE
    (*

    Machine Check Exception

    *)
  9. | `CX8
    (*

    CMPXCHG8 instruction

    *)
  10. | `APIC
    (*

    Onboard APIC

    *)
  11. | `SEP
    (*

    SYSENTER/SYSEXIT

    *)
  12. | `MTRR
    (*

    Memory Type Range Registers

    *)
  13. | `PGE
    (*

    Page Global Enable

    *)
  14. | `MCA
    (*

    Machine Check Architecture

    *)
  15. | `CMOV
    (*

    CMOV instructions

    *)
  16. | `PAT
    (*

    Page Attribute Table

    *)
  17. | `PSE36
    (*

    36-bit PSEs

    *)
  18. | `PN
    (*

    Processor serial number

    *)
  19. | `CLFLUSH
    (*

    CLFLUSH instruction

    *)
  20. | `DTS
    (*

    Debug Store

    *)
  21. | `ACPI
    (*

    ACPI via MSR

    *)
  22. | `MMX
    (*

    Multimedia Extensions

    *)
  23. | `FXSR
    (*

    FXSAVE/FXRSTOR, CR4.OSFXSR

    *)
  24. | `SSE
    (*

    SSE

    *)
  25. | `SSE2
    (*

    SSE2

    *)
  26. | `SS
    (*

    CPU self snoop

    *)
  27. | `HT
    (*

    Hyper-Threading

    *)
  28. | `TM
    (*

    Automatic clock control

    *)
  29. | `IA64
    (*

    IA-64 processor

    *)
  30. | `PBE
    (*

    Pending Break Enable

    *)
  31. | `SYSCALL
    (*

    SYSCALL/SYSRET

    *)
  32. | `MP
    (*

    MP Capable.

    *)
  33. | `NX
    (*

    Execute Disable

    *)
  34. | `MMXEXT
    (*

    AMD MMX extensions

    *)
  35. | `FXSR_OPT
    (*

    FXSAVE/FXRSTOR optimizations

    *)
  36. | `PDPE1GB
    (*

    GB pages

    *)
  37. | `RDTSCP
    (*

    RDTSCP

    *)
  38. | `LM
    (*

    Long Mode (x86-64)

    *)
  39. | `F_3DNOWEXT
    (*

    AMD 3DNow! extensions

    *)
  40. | `F_3DNOW
    (*

    3DNow!

    *)
  41. | `PNI
    (*

    SSE-3

    *)
  42. | `PCLMULQDQ
    (*

    PCLMULQDQ instruction

    *)
  43. | `DTES64
    (*

    64-bit Debug Store

    *)
  44. | `MONITOR
    (*

    Monitor/Mwait support

    *)
  45. | `DS_CPL
    (*

    CPL Qual. Debug Store

    *)
  46. | `VMX
    (*

    Hardware virtualization

    *)
  47. | `SMX
    (*

    Safer mode

    *)
  48. | `EST
    (*

    Enhanced SpeedStep

    *)
  49. | `TM2
    (*

    Thermal Monitor 2

    *)
  50. | `SSSE3
    (*

    Supplemental SSE-3

    *)
  51. | `CID
    (*

    Context ID

    *)
  52. | `SDBG
    (*

    Silicon Debug

    *)
  53. | `FMA
    (*

    Fused multiply-add

    *)
  54. | `CX16
    (*

    CMPXCHG16B

    *)
  55. | `XTPR
    (*

    Send Task Priority Messages

    *)
  56. | `PDCM
    (*

    Performance Capabilities

    *)
  57. | `PCID
    (*

    Process Context Identifiers

    *)
  58. | `DCA
    (*

    Direct Cache Access

    *)
  59. | `SSE4_1
    (*

    SSE-4.1

    *)
  60. | `SSE4_2
    (*

    SSE-4.2

    *)
  61. | `X2APIC
    (*

    x2APIC

    *)
  62. | `MOVBE
    (*

    MOVBE instruction

    *)
  63. | `POPCNT
    (*

    POPCNT instruction

    *)
  64. | `TSC_DEADLINE_TIMER
    (*

    Tsc deadline timer

    *)
  65. | `AES
    (*

    AES instructions

    *)
  66. | `XSAVE
    (*

    XSAVE/XRSTOR/XSETBV/XGETBV

    *)
  67. | `OSXSAVE
    (*

    XSAVE enabled in the OS

    *)
  68. | `AVX
    (*

    Advanced Vector Extensions

    *)
  69. | `F16C
    (*

    16-bit fp conversions

    *)
  70. | `RDRAND
    (*

    The RDRAND instruction

    *)
  71. | `HYPERVISOR
    (*

    Running on a hypervisor

    *)
  72. | `LAHF_LM
    (*

    LAHF/SAHF in long mode

    *)
  73. | `CMP_LEGACY
    (*

    If yes HyperThreading not valid

    *)
  74. | `SVM
    (*

    Secure virtual machine

    *)
  75. | `EXTAPIC
    (*

    Extended APIC space

    *)
  76. | `CR8_LEGACY
    (*

    CR8 in 32-bit mode

    *)
  77. | `ABM
    (*

    Advanced bit manipulation

    *)
  78. | `SSE4A
    (*

    SSE-4A

    *)
  79. | `MISALIGNSSE
    (*

    Misaligned SSE mode

    *)
  80. | `F_3DNOWPREFETCH
    (*

    3DNow prefetch instructions

    *)
  81. | `OSVW
    (*

    OS Visible Workaround

    *)
  82. | `IBS
    (*

    Instruction Based Sampling

    *)
  83. | `XOP
    (*

    extended AVX instructions

    *)
  84. | `SKINIT
    (*

    SKINIT/STGI instructions

    *)
  85. | `WDT
    (*

    Watchdog timer

    *)
  86. | `LWP
    (*

    Light Weight Profiling

    *)
  87. | `FMA4
    (*

    4 operands MAC instructions

    *)
  88. | `TCE
    (*

    translation cache extension

    *)
  89. | `NODEID_MSR
    (*

    NodeId MSR

    *)
  90. | `TBM
    (*

    trailing bit manipulations

    *)
  91. | `TOPOEXT
    (*

    topology extensions CPUID leafs

    *)
  92. | `PERFCTR_CORE
    (*

    core performance counter extensions

    *)
  93. | `PERFCTR_NB
    (*

    NB performance counter extensions

    *)
  94. | `BPEXT
    (*

    data breakpoint extension

    *)
  95. | `PTSC
    (*

    performance time-stamp counter

    *)
  96. | `PERFCTR_L2
    (*

    L2 performance counter extensions

    *)
  97. | `MWAITX
    (*

    MWAIT extension (MONITORX/MWAITX)

    *)
  98. | `FSGSBASE
    (*

    {RD/WR}{FS/GS}BASE instructions

    *)
  99. | `TSC_ADJUST
    (*

    TSC adjustment MSR 0x3b

    *)
  100. | `BMI1
    (*

    1st group bit manipulation extensions

    *)
  101. | `HLE
    (*

    Hardware Lock Elision

    *)
  102. | `AVX2
    (*

    AVX2 instructions

    *)
  103. | `SMEP
    (*

    Supervisor Mode Execution Protection

    *)
  104. | `BMI2
    (*

    2nd group bit manipulation extensions

    *)
  105. | `ERMS
    (*

    Enhanced REP MOVSB/STOSB

    *)
  106. | `INVPCID
    (*

    Invalidate Processor Context ID

    *)
  107. | `RTM
    (*

    Restricted Transactional Memory

    *)
  108. | `CQM
    (*

    Cache QoS Monitoring

    *)
  109. | `MPX
    (*

    Memory Protection Extension

    *)
  110. | `AVX512F
    (*

    AVX-512 Foundation

    *)
  111. | `AVX512DQ
    (*

    AVX-512 DQ (Double/Quad granular) Instructions

    *)
  112. | `RDSEED
    (*

    The RDSEED instruction

    *)
  113. | `ADX
    (*

    The ADCX and ADOX instructions

    *)
  114. | `SMAP
    (*

    Supervisor Mode Access Prevention

    *)
  115. | `CLFLUSHOPT
    (*

    CLFLUSHOPT instruction

    *)
  116. | `CLWB
    (*

    CLWB instruction

    *)
  117. | `AVX512PF
    (*

    AVX-512 Prefetch

    *)
  118. | `AVX512ER
    (*

    AVX-512 Exponential and Reciprocal

    *)
  119. | `AVX512CD
    (*

    AVX-512 Conflict Detection

    *)
  120. | `SHA_NI
    (*

    SHA1/SHA256 Instruction Extensions

    *)
  121. | `AVX512BW
    (*

    AVX-512 BW (Byte/Word granular) Instructions

    *)
  122. | `AVX512VL
    (*

    AVX-512 VL (128/256 Vector Length) Extensions

    *)
  123. | `PKU
    (*

    Protection Keys for Userspace

    *)
  124. | `OSPKE
    (*

    OS Protection Keys Enable

    *)
]

CPU flags signify presence of individual features.

Consult the interface file for the meaning of individual flags.

val pp_error : Format.formatter -> error -> unit

pp_error ppf e formats the error e to the formatter ppf.

val pp_vendor : Format.formatter -> vendor -> unit

pp_vendor ppf v formats the vendor v to the formatter ppf.

val pp_flag : Format.formatter -> flag -> unit

pp_flag ppf f formats the flag f to the formatter ppf.

Queries

val vendor : unit -> vendor result

vendor () is the CPU vendor, or an error.

val model : unit -> (int * int * int) result

model () is the CPU's family, model and stepping, or an error.

val flags : unit -> flag list result

flags () is the list of CPU flags, or an error.

val supports : flag list -> bool result

supports fs is true iff all fs are in flags ().

val cores : unit -> int result

cores () is the number of available logical cores.

Note Do not take cores () too seriously. See limitations.