package hardcaml_xilinx

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package hardcaml_xilinx
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Source file dual_port_ram.ml

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open! Base
open! Hardcaml

let create
  ?read_latency
  ?arch
  ?byte_write_width
  ?memory_optimization
  ?cascade_height
  ?simulation_name
  ~build_mode
  ()
  ~clock
  ~clear
  ~size
  ~port_a
  ~port_b
  =
  True_dual_port_ram.create
    ?read_latency
    ?arch
    ?byte_write_width
    ~build_mode
    ?memory_optimization
    ?cascade_height
    ?simulation_name
    ()
    ~clock_a:clock
    ~clock_b:clock
    ~clear_a:clear
    ~clear_b:clear
    ~size
    ~port_a
    ~port_b
;;