package hardcaml_verilator

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Hardcaml Verilator Simulation Backend

Install 

dune-project
 Dependency

github.com Readme Changelog MIT License Edit opam file Versions (3)

Authors

  1. J
    Jane Street Group, LLC

Maintainers

  1. J
    Jane Street developers

Sources

v0.17.0.tar.gz
sha256=76f944f35c445eeb3028ff9e73dcdf1778937078ad655c1e949278d23d888251

doc/hardcaml_verilator/Hardcaml_verilator/index.html

Module Hardcaml_verilatorSource

Verilator backend for Hardcaml cycle simulations.

While this performs faster than Hardcaml's Cyclesim, it takes a longer time to elaborate the design (a ~3_000 LoC verilog file takes around 2 seconds, whilist hardcaml's Cyclesim takes 0.1 second). The default is to run it in non-thread safe mode (ie: single threaded w/o atomics / locks), which is the preferred option for small designs. The create and With_interface.create functions do the following:

0. Generates the verilog file of the circuit 1. Calls verilator to generate C++ file for simulation 3. Generates C-wrapper for accessing fields in the C++ data structure 4. Compiles the generated C++ file and C-wrapper to make a shared library 5. Dyanmically load the shared library back to the same executable and bind the > functions using C-types 6. Create a Cyclesim.t instance by supplying the relevant functions with bindings to > verilator

Sourcemodule Optimization_level : sig ... end
Sourcemodule Threads : sig ... end
Sourcemodule Output_split : sig ... end
Sourcemodule Verilator_version : sig ... end
Sourcemodule Config : sig ... end
Sourcemodule Cache : sig ... end
Sourcemodule Simulation_backend : sig ... end
Sourcetype input_port = Hardcaml.Bits.t -> unit
Sourcetype output_port = unit -> Hardcaml.Bits.t
Sourcetype internal_port = {
  1. signal : Hardcaml.Signal.t;
  2. bits : Hardcaml.Bits.Mutable.t;
  3. update : unit -> unit;
  4. aliases : string list;
}
Sourcetype t = {
  1. input_setters : (string, input_port) Core.List.Assoc.t;
  2. output_getters : (string, output_port) Core.List.Assoc.t;
  3. internal_getters : (string, internal_port) Core.List.Assoc.t;
  4. eval : unit -> unit;
  5. complete : unit -> unit;
}
Sourcetype 'a with_options = ?cache:Cache.t -> ?build_dir:string -> ?verilator_config:Config.t -> ?config:Hardcaml.Cyclesim.Config.t -> 'a

Arguments when creating a verilator simulation object.

  • cache specifies whether and where to store compiled shared libraries. When set to a directory, the create functions below first tries to check if an existing compilation for the current circuit exists in the specified directory. When set to a file, the file is used directly as the shared library. This can speed up compilation for repeated simulation runs.
  • build_dir specifies the build directory. Defaults to somewhere in /tmp.
  • optimizations specifies whether verilator optimizations should be turned on.
  • parallel_compile specifies whether the verilator simulation object should be compiled in parallel, and if so with how many parallel jobs.
  • threads speficies whether the verilator simulation object should be generated to be run in parallel, and if so with how many parallel threads.
  • version specifies which major version of verilator we want to use.
Sourceval compile_circuit_and_load_shared_object : (Hardcaml.Circuit.t -> t) with_options
Sourceval create : (clock_names:string list -> Hardcaml.Circuit.t -> Hardcaml.Cyclesim.t_port_list) with_options