package hardcaml_step_testbench

You can search for identifiers within the package.

in-package search v0.2.0

hardcaml_step_testbench
- Hardcaml_step_testbench
  - Before_and_after_edge
  - Make
    
    Array
    
    I
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    I_data
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Monad_infix
    
    O
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O_data
    
    Simulator
  - S
    
    Array
    
    I
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    I_data
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    List
    
    Monad_infix
    
    O
    
    All
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O_data
    
    Simulator
hardcaml_step_testbench.digital_components
- Digital_components
  - Component
    
    Combinational
    
    S
    
    Input
    
    Output
    
    Flip_flop_with_load_enable
    
    Input
    
    Flip_flop_with_load_enable_and_reset
    
    Input
    
    Next_input
    
    S
    
    Input
    
    Output
  - Data
    
    Bool
    
    Int
    
    Pair
    
    D1
    
    D2
    
    S
    
    String
    
    Unit
  - Step_monad
    
    Component_finished
    
    Event
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix

Legend:
Library
Module
Module type
Parameter
Class
Class type

type ('a, 'i, 'o) t

val sexp_of_t : 
  ('a -> Sexplib0.Sexp.t) ->
  ('i -> Sexplib0.Sexp.t) ->
  ('o -> Sexplib0.Sexp.t) ->
  ('a, 'i, 'o) t ->
  Sexplib0.Sexp.t

val (>>=) : ('a, 'd, 'e) t -> ('a -> ('b, 'd, 'e) t) -> ('b, 'd, 'e) t

val (>>|) : ('a, 'd, 'e) t -> ('a -> 'b) -> ('b, 'd, 'e) t

module Let_syntax : sig ... end

module Monad_infix : sig ... end

val bind : ('a, 'd, 'e) t -> f:('a -> ('b, 'd, 'e) t) -> ('b, 'd, 'e) t

val return : 'a -> ('a, 'b, 'c) t

val map : ('a, 'd, 'e) t -> f:('a -> 'b) -> ('b, 'd, 'e) t

val join : (('a, 'd, 'e) t, 'd, 'e) t -> ('a, 'd, 'e) t

val ignore_m : ('a, 'd, 'e) t -> (unit, 'd, 'e) t

val all : ('a, 'd, 'e) t list -> ('a list, 'd, 'e) t

val all_unit : (unit, 'd, 'e) t list -> (unit, 'd, 'e) t

val next_step : 
  Digital_components__.Import.Source_code_position.t ->
  'o ->
  ('i, 'i, 'o) t

val thunk : 
  (Digital_components__.Import.Unit.t -> ('a, 'i, 'o) t) ->
  ('a, 'i, 'o) t

val output_forever : 'o -> (_, _, 'o) t

val for_ : 
  Digital_components__.Import.Int.t ->
  Digital_components__.Import.Int.t ->
  (Digital_components__.Import.Int.t ->
    (Digital_components__.Import.Unit.t, 'i, 'o) t) ->
  (Digital_components__.Import.Unit.t, 'i, 'o) t

for_ i j f does f i, f (i+1), ... f j in sequence. If j < i, then for_ i j immediately returns unit.

val delay : 
  'o ->
  num_steps:Digital_components__.Import.Int.t ->
  (Digital_components__.Import.Unit.t, _, 'o) t

delay o ~num_steps outputs o for num_steps and then returns unit. delay raises if num_steps < 0.

val repeat : 
  count:Digital_components__.Import.Int.t ->
  (Digital_components__.Import.Unit.t ->
    (Digital_components__.Import.Unit.t, 'i, 'o) t) ->
  (Digital_components__.Import.Unit.t, 'i, 'o) t

repeat ~count f does f () count times. repeat raises if count < 0.

val wait : 
  output:'o ->
  until:('i -> Digital_components__.Import.Bool.t) ->
  (Digital_components__.Import.Unit.t, 'i, 'o) t

module Event : sig ... end

An event is a value that will at some point in time (possibly the past, possibly the future) transition from "undetermined" to "determined", with some value. One can wait_for an event in a computation.

val wait_for : 'a Event.t -> output:'o -> ('a, _, 'o) t

wait_for event ~output outputs output until the step at which event becomes determined, at which point the wait_for proceeds.

module Component_finished : sig ... end

val spawn : 
  ?update_children_after_finish:Digital_components__.Import.Bool.t ->
  Digital_components__.Import.Source_code_position.t ->
  start:('i_c -> (('a, 'o_c) Component_finished.t, 'i_c, 'o_c) t) ->
  input:'i_c Data.t ->
  output:'o_c Data.t ->
  child_input:(parent:'i -> 'i_c) ->
  include_child_output:(parent:'o -> child:'o_c -> 'o) ->
  (('a, 'o_c) Component_finished.t Event.t, 'i, 'o) t

spawn creates a child computation that runs start. spawn returns on the current step, and the child starts on the next step. The parent computation uses child_input to adjust its input into the form that the child computation sees, and include_child_output to incorporate the child's output into its output.

When update_children_after_finish, unfinished tasks spawned from within start will be executed even after start completes.

val create_component : 
  created_at:Digital_components__.Import.Source_code_position.t ->
  update_children_after_finish:Digital_components__.Import.Bool.t ->
  start:('i -> (('a, 'o) Component_finished.t, 'i, 'o) t) ->
  input:'i Data.t ->
  output:'o Data.t ->
  ('i, 'o) Component.t * ('a, 'o) Component_finished.t Event.t

create_component creates a Component.t that runs the computation described by start. When update_children_after_finish is set to true, all component's children will be updated even after the child terminates. This will result in tasks spawned from within the child task to execute even after the child terminates.