package hardcaml_step_testbench

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package hardcaml_step_testbench
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Module
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module Monads : sig ... end
module Simulator : sig ... end
module type S = sig ... end
include S
include Imperative.S with module Step_monad = Monads.Step_monad
module No_data : Digital_components.Data.S with type t = unit
module Step_monad = Monads.Step_monad
type 'a t = ('a, No_data.t, No_data.t) Step_monad.t
include Core.Monad.S with type 'a t := 'a t
val (>>=) : 'a t -> ('a -> 'b t) -> 'b t

t >>= f returns a computation that sequences the computations represented by two monad elements. The resulting computation first does t to yield a value v, and then runs the computation returned by f v.

val (>>|) : 'a t -> ('a -> 'b) -> 'b t

t >>| f is t >>= (fun a -> return (f a)).

module Monad_infix : sig ... end
val bind : 'a t -> f:('a -> 'b t) -> 'b t

bind t ~f = t >>= f

val return : 'a -> 'a t

return v returns the (trivial) computation that returns v.

val map : 'a t -> f:('a -> 'b) -> 'b t

map t ~f is t >>| f.

val join : 'a t t -> 'a t

join t is t >>= (fun t' -> t').

val ignore_m : 'a t -> unit t

ignore_m t is map t ~f:(fun _ -> ()). ignore_m used to be called ignore, but we decided that was a bad name, because it shadowed the widely used Stdlib.ignore. Some monads still do let ignore = ignore_m for historical reasons.

val all : 'a t list -> 'a list t
val all_unit : unit t list -> unit t

Like all, but ensures that every monadic value in the list produces a unit value, all of which are discarded rather than being collected into a list.

module Let_syntax : sig ... end

These are convenient to have in scope when programming with a monad:

val cycle : ?num_cycles:int -> unit -> unit t

cycle i_data ~num_cycles waits for num_cycles cycles of the simulator to run. cycle raises if num_cycles < 1.

val for_ : int -> int -> (int -> unit t) -> unit t

for_ i j f does f i, f (i+1), ... f j in sequence. If j < i, then for_ i j immediately returns unit.

val start : ('a -> 'b t) -> 'a -> ('b, No_data.t) Step_monad.Component_finished.t t
type 'a finished_event = ('a, unit) Step_monad.Component_finished.t Step_monad.Event.t
val spawn : (unit -> 'a t) -> 'a finished_event t

Launch a new task within the current simulation step.

val wait_for : 'a finished_event -> 'a t

Wait for the given event to occur, and extract its return value.

val wait_for_with_timeout : 'a finished_event -> timeout_in_cycles:int -> 'a option t

Like wait_for except it stops waiting after timeout_in_cycles and returns None. Note that the spawned task continues to execute.

module List : sig ... end
module Array : sig ... end
module Simulation_step : sig ... end
type ('a, 'r) run = ?timeout:int -> ?simulation_step:Simulation_step.t -> unit -> clock: Hardcaml_event_driven_sim.Two_state_logic.t Event_driven_sim.Simulator.Signal.t -> testbench:(unit -> 'a t) -> 'r
val deferred : ('a, unit -> 'a option Event_driven_sim.Simulator.Async.Deferred.t) run

Create an event sim deferred that can be run inside a process. The result of the step testbench is returned. None is returned if the simulation times out.

The clock signal should be driven externally - do NOT set it within the step moand.

Wrap an event sim in a process and wait forever after it completes.

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