package hardcaml_step_testbench

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Module Imperative.Event_driven_simSource

Sourcemodule Monads : sig ... end
Sourcemodule Simulator : sig ... end
Sourcemodule type S = sig ... end
include S
include Imperative.S with module Step_monad = Monads.Step_monad
Sourcemodule No_data : Digital_components.Data.S with type t = unit
Sourcemodule Step_monad = Monads.Step_monad
include Core.Monad.S with type 'a t := 'a t
val (>>=) : 'a t -> ('a -> 'b t) -> 'b t
val (>>|) : 'a t -> ('a -> 'b) -> 'b t
module Monad_infix : sig ... end
val bind : 'a t -> f:('a -> 'b t) -> 'b t
val return : 'a -> 'a t
val map : 'a t -> f:('a -> 'b) -> 'b t
val join : 'a t t -> 'a t
val ignore_m : 'a t -> unit t
val all : 'a t list -> 'a list t
val all_unit : unit t list -> unit t
module Let_syntax : sig ... end
Sourceval cycle : ?num_cycles:int -> unit -> unit t

cycle i_data ~num_cycles waits for num_cycles cycles of the simulator to run. cycle raises if num_cycles < 1.

Sourceval for_ : int -> int -> (int -> unit t) -> unit t

for_ i j f does f i, f (i+1), ... f j in sequence. If j < i, then for_ i j immediately returns unit.

Sourceval start : ('a -> 'b t) -> 'a -> ('b, No_data.t) Step_monad.Component_finished.t t
Sourcetype 'a finished_event = ('a, unit) Step_monad.Component_finished.t Step_monad.Event.t
Sourceval spawn : (unit -> 'a t) -> 'a finished_event t

Launch a new task within the current simulation step.

Sourceval wait_for : 'a finished_event -> 'a t

Wait for the given event to occur, and extract its return value.

Sourceval wait_for_with_timeout : 'a finished_event -> timeout_in_cycles:int -> 'a option t

Like wait_for except it stops waiting after timeout_in_cycles and returns None. Note that the spawned task continues to execute.

Sourcemodule List : sig ... end
Sourcemodule Array : sig ... end
Sourcemodule Simulation_step : sig ... end
Sourcetype ('a, 'r) run = ?timeout:int -> ?simulation_step:Simulation_step.t -> unit -> clock: Hardcaml_event_driven_sim.Two_state_logic.t Hardcaml_step_testbench__.Imperative_event_driven_sim_intf.Simulator.Event_simulator.Signal.t -> testbench:(unit -> 'a t) -> 'r
Sourceval deferred : ('a, unit -> 'a option Hardcaml_step_testbench__.Imperative_event_driven_sim_intf.Simulator.Event_simulator.Async.Deferred.t) run

Create an event sim deferred that can be run inside a process. The result of the step testbench is returned. None is returned if the simulation times out.

The clock signal should be driven externally - do NOT set it within the step moand.

Sourceval process : (unit, Hardcaml_step_testbench__.Imperative_event_driven_sim_intf.Simulator.Event_simulator.Process.t) run

Wrap an event sim in a process and wait forever after it completes.