package hardcaml_step_testbench

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package hardcaml_step_testbench
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include Functional.S with module Step_monad = Hardcaml_step_testbench__.Functional_cyclesim_intf.Monads.Step_monad with module I = I with module O = O with module Step_monad = Monads.Step_monad
module Step_monad = Monads.Step_monad
module I = I
module O = O
module O_data : sig ... end
type 'a t = ('a, O_data.t, I_data.t) Step_monad.t

A testbench takes the circuit's output as its input and produces its output as input for the circuit. An 'a t describes a testbench computation that takes zero or more steps and produces a value of type 'a.

include Core.Monad.S with type 'a t := 'a t
val (>>=) : 'a t -> ('a -> 'b t) -> 'b t

t >>= f returns a computation that sequences the computations represented by two monad elements. The resulting computation first does t to yield a value v, and then runs the computation returned by f v.

val (>>|) : 'a t -> ('a -> 'b) -> 'b t

t >>| f is t >>= (fun a -> return (f a)).

module Monad_infix : sig ... end
val bind : 'a t -> f:('a -> 'b t) -> 'b t

bind t ~f = t >>= f

val return : 'a -> 'a t

return v returns the (trivial) computation that returns v.

val map : 'a t -> f:('a -> 'b) -> 'b t

map t ~f is t >>| f.

val join : 'a t t -> 'a t

join t is t >>= (fun t' -> t').

val ignore_m : 'a t -> unit t

ignore_m t is map t ~f:(fun _ -> ()). ignore_m used to be called ignore, but we decided that was a bad name, because it shadowed the widely used Stdlib.ignore. Some monads still do let ignore = ignore_m for historical reasons.

val all : 'a t list -> 'a list t
val all_unit : unit t list -> unit t

Like all, but ensures that every monadic value in the list produces a unit value, all of which are discarded rather than being collected into a list.

module Let_syntax : sig ... end

These are convenient to have in scope when programming with a monad:

val start : ('a -> 'b t) -> 'a -> ('b, I_data.t) Step_monad.Component_finished.t t
val cycle : ?num_cycles:int -> I_data.t -> O_data.t t

cycle i_data ~num_cycles waits for num_cycles cycles of the simulator to run, applying i_data to the simulator input ports, and returns the output computed in the final cycle. cycle raises if num_cycles < 1.

val for_ : int -> int -> (int -> unit t) -> unit t

for_ i j f does f i, f (i+1), ... f j in sequence. If j < i, then for_ i j immediately returns unit.

val delay : I_data.t -> num_cycles:int -> unit t

delay inputs ~num_cycles applies inputs for num_cycles clock cycles and then returns unit. delay raises if num_cycles < 0.

type ('a, 'b) finished_event = ('a, 'b) Step_monad.Component_finished.t Step_monad.Event.t
val spawn : (O_data.t -> 'a t) -> ('a, I_data.t) finished_event t

Launch a new task within the current simulation step.

val merge_inputs : parent:I_data.t -> child:I_data.t -> I_data.t

merge_inputs ~parent ~child merges the child inputs into the parent. If a child input is empty, the parent's value is used.

val spawn_io : inputs:(parent:'i -> child:I_data.t -> 'i) -> outputs:('o -> Hardcaml.Bits.t O.t) -> (O_data.t -> 'a t) -> (('a, I_data.t) finished_event, 'o Before_and_after_edge.t, 'i) Step_monad.t

Launch a task from a testbench with a cycle function taking 'i to 'o. The inputs and outputs arguments should construct I_data.t and O_data.t from the types of the child testbench.

val wait_for : ('a, 'b) finished_event -> 'a t

Wait for the given event to occur, and extract its return value.

val wait_for_with_timeout : ('a, 'b) finished_event -> timeout_in_cycles:int -> 'a option t

Like wait_for except it stops waiting after timeout_in_cycles and returns None. Note that the spawned task continues to execute.

val input_hold : Hardcaml.Bits.t I.t

Call run ~input_default:input_hold to hold inputs their previous value if they are unset by tasks in the testbench.

val input_zero : Hardcaml.Bits.t I.t

Call run ~input_default:input_zero to set inputs to zero if unset by tasks in the testbench.

module List : sig ... end
module Array : sig ... end
module Simulator : sig ... end

A simulator for the design being tested.

val run_with_timeout : ?input_default:Hardcaml.Bits.t I.t -> ?update_children_after_finish:bool -> ?show_steps:bool -> ?timeout:int -> unit -> simulator:Simulator.t -> testbench:(O_data.t -> 'a t) -> 'a option

Run the testbench until the main task finishes. The input_default argument controls what should happen if an input is unset by tasks in the testbench on any particular cycle. If a field is set to Bits.empty then the previous value should be held. Otherwise, the value provided is used as the default value for that field.

The optional timeout argument stops the simulation after the given number of steps and returns None. Otherwise it will continue until the testbech completes.

val run_until_finished : ?input_default:Hardcaml.Bits.t I.t -> ?show_steps:bool -> ?update_children_after_finish:bool -> unit -> simulator:Simulator.t -> testbench:(O_data.t -> 'a t) -> 'a

Run the testbench until completion.

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