Arbiter circuits. Given a set of requesters the arbiter chooses one to succeed.

Coordinate rotation digital computer.

Reference implementation of the CORDIC algorithm using Float.t.

CORDIC implementations of various different functions.

Register stage with up and downstream valid/ready control.

A counter. If the current value is n, it outputs n/divisor (as quotient) and n mod divisor (as remainder). Since the counter doesn't track n directly, the maximum values must be specified as max_quotient and max_remainder, and the counter will wrap when its outputs reach max_quotient AND max_remainder.

Low latency combinational fifo. See create for documentation.

Linear feedback shift registers

Calculate x % y where x >= 0 and y > 0.

Wallace/Dadda tree multipliers.

Convert an arbitrary input vector to onehot. The first bit set scanning from either the lsb or msb will be set in the output and all others will be 0. The architecture has logarithmic delay.

Pipelined adder architectures for very wide adders.

Simple pipelined incrementer.

Pipelined tree reduce operation, with propogation delay equivalent to ceil(log(|args|))

Parallel prefix networks. See https://en.wikipedia.org/wiki/Prefix_sum.

ROM-accumulator.

Sorting networks.

Synchronous stack implementation

Represents a computation broken into multiple stages. Each stage is returned in an array.

A simple vector structure with insert and delete operations at arbitrary positions.