package hardcaml_circuits

  1. Overview
  2. Docs
package hardcaml_circuits
Legend:
Library
Module
Module type
Parameter
Class
Class type

Pipelined adder with a constant 2 cycle latency.

Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca. Pipelined FPGA Adders. International Conference on Field Programmable Logic and Applications, Aug 2010, Milano, Italy. pp.422-427, ff10.1109/FPL.2010.87ff. ffensl-00475780v2f

There is an output combinational delay of a single adder:

width / part_width.

The maximum delay is an adder of width:

max (width / part_width) (part_width*2)

val comb : (module Hardcaml.Comb.S with type t = 'a) -> part_width:Base.int -> 'a -> 'a -> 'a

Combinational version of the circuit. For testing.

Sequential circuit with 2 cycle delay.

OCaml

Innovation. Community. Security.

GitHub Discord Twitter Peertube RSS
About
Changelog Releases Industrial Users Academic Users Why OCaml
Ecosystem
Packages Community Events OCaml Planet Jobs
Resources
Install OCaml Get Started Platform Tools Language Manual Standard Library API Books Exercises Papers OCaml Playground Logo
Policies
Carbon Footprint Governance Privacy Code of Conduct