package hardcaml_c

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Parameters
Signature

package hardcaml_c

hardcaml_c
- Hardcaml_c
  - Cyclesim
    
    With_interface
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    TypedMath
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Instance

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Library
Module
Module type
Parameter
Class
Class type

Parameters

module I : Hardcaml.Interface.S

module O : Hardcaml.Interface.S

Signature

type t =
  (Hardcaml.Bits.t Stdlib.ref I.t, Hardcaml.Bits.t Stdlib.ref O.t)
    Hardcaml.Cyclesim.t

val create : 
  ?config:Hardcaml.Cyclesim.Config.t ->
  ?circuit_config:Hardcaml.Circuit.Config.t ->
  ?combine_with_cyclesim:bool ->
  ?compiler_command:string ->
  Hardcaml.Circuit.With_interface(I)(O).create ->
  t

Create a simulator using the provided Create_fn. The returned simulator ports are coerced to the input and output interface types.

val coerce : Hardcaml.Cyclesim.t_port_list -> t

Coerce simulator port types to use the provided input and output interfaces.