A simplified protocol for reading from and writing to slave space within a hardware design. Reads and writes are framed by _valid and _first signals. The _valid signal will be high throughout the transaction, while _first will toggle high only on the first cycle of a transaction. The _ready signals, driven by the slave, indicate completion of a transaction.

Statemachine for conversion between AXI transfers, and the simplified protocol defined by Internal_bus

Convert a single AXI address range into multiple interface slave spaces.

RAM with per byte enable and configurable size

Register bank attached directly to the AXI bus. Under the hood, this uses Internal_bus.Register_bank