VHDL and Verilog netlist generation
module Language : sig ... endmodule Output_mode : sig ... endRTL generation options.
module Blackbox : sig ... endControl blackbox generation. None implies blackboxes are not used. Top means the circuit will be turned into a blackbox. Instantiations means that the top level circuit will be written as normal, but submodules will be written as blackboxes.
val output :
?output_mode:Output_mode.t ->
?database:Circuit_database.t ->
?blackbox:Blackbox.t ->
Language.t ->
Circuit.t ->
Hardcaml__.Import.Unit.tWrite circuit to Verilog or Vhdl. Instantiations are (recursively) looked up in database and if a circuit exists it is also written. The output_mode specifies how the circuit should be written - either to a single file (or buffer, or channel) or to a directory with one file for each for the top level circuit and any instantiated circuits contained in the database.
val print :
?database:Circuit_database.t ->
?blackbox:Blackbox.t ->
Language.t ->
Circuit.t ->
Hardcaml__.Import.Unit.tprint is output ~output_mode:(To_channel stdout)