package hardcaml

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package hardcaml
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Module Hardcaml.ParameterSource

A Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.

In Verilog they are called parameterss and in VHDL they are called generics.

Sourcemodule Std_logic : sig ... end

9-state VHDL std_logic enumeration

Sourcemodule Std_logic_vector : sig ... end
Sourcemodule Bit_vector : sig ... end
Sourcemodule Value : sig ... end
Sourcetype t = {
  1. name : Parameter_name.t;
  2. value : Value.t;
}
Sourceval compare : t -> t -> Base.Int.t
Sourceval sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
include Base.Equal.S with type t := t
Sourcemodule Unstable : sig ... end
Sourceval create : name:Base.String.t -> value:Value.t -> t
Sourceval find_name_exn : t Base.List.t -> Parameter_name.t -> Value.t

is_subset ts1 ts2 returns true iff every t in ts1 is in ts2.

Sourceval sort_by_name : t Base.List.t -> t Base.List.t
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