Module `Hardcaml.Cyclesim`Source

Cycle accurate simulator

Sourcemodule Port_list : sig ... end

Sourcetype ('i, 'o) t

base type of the cycle based simulators

Sourcetype t_port_list = (Port_list.t, Port_list.t) t

Sourceval scheduling_deps : Signal.t -> Signal.t Base.List.t

Specialised signal dependencies that define a graph that breaks cycles through sequential elements. This is done by removing the input edges of registers and memories (excluding the read address, since hardcaml memories are read asynchronously).

Instantiations do not allow cycles from output to input ports, which is a valid assumption for the simulator, but not in general.

Note that all signals in the graph cannot be reached from just the outputs of a circuit using these dependencies. The (discarded) inputs to all registers and memories must also be included.

Sourceval cycle : (_, _) t -> Base.Unit.t

advance by 1 clock cycle (check->comb->seq->comb)

Sourceval cycle_check : (_, _) t -> Base.Unit.t

check inputs are valid before a simulation cycle

Sourceval cycle_before_clock_edge : (_, _) t -> Base.Unit.t

update combinatorial logic before clock edge and relative to new inputs.

Sourceval cycle_at_clock_edge : (_, _) t -> Base.Unit.t

update sequential logic - registers and memories.

Sourceval cycle_after_clock_edge : (_, _) t -> Base.Unit.t

update combinatorial logic after clock edge

Sourceval reset : (_, _) t -> Base.Unit.t

reset simulator

Sourceval in_port : (_, _) t -> Base.String.t -> Bits.t Base.Ref.t

get input port given a name

Source

val out_port : 
  ?clock_edge:Side.t ->
  (_, _) t ->
  Base.String.t ->
  Bits.t Base.Ref.t

Get output port given a name. If clock_edge is Before the outputs are computed prior to the clock edge - After means the outputs are computed after the clock edge.

Sourceval inputs : ('i, _) t -> 'i

Sourceval outputs : ?clock_edge:Side.t -> (_, 'o) t -> 'o

Sourceval in_ports : (_, _) t -> Port_list.t

Sourceval out_ports : ?clock_edge:Side.t -> (_, _) t -> Port_list.t

Sourceval internal_ports : (_, _) t -> Port_list.t

get list of internal nodes

Sourceval lookup_signal : (_, _) t -> Signal.Uid.t -> Bits.t Base.Ref.t

Sourceval lookup_reg : (_, _) t -> Signal.Uid.t -> Bits.t Base.Ref.t

Source

type 'a with_create_options =
  ?is_internal_port:(Signal.t -> Base.Bool.t) ->
  ?combinational_ops_database:Combinational_ops_database.t ->
  'a

Sourceval create : (Circuit.t -> t_port_list) with_create_options

construct a simulator from a circuit

Sourcemodule Combine_error : sig ... end

Source

val combine : 
  ?port_sets_may_differ:Base.Bool.t ->
  ?on_error:(Combine_error.t -> Base.Unit.t) ->
  ('i, 'o) t ->
  ('i, 'o) t ->
  ('i, 'o) t

Combine 2 simulators. The inputs are set on the 1st simulator and copied to the 2nd. Outputs are checked and on_error is called if a difference is found. By default, on_error raises.

The simulators should have the same input and output port sets, unless port_sets_may_differ is true, in which case only ports which exist on both simulators are checked.

Sourcemodule With_interface (I : Interface.S) (O : Interface.S) : sig ... end

Sourcemodule Private : sig ... end

package hardcaml

Module Hardcaml.CyclesimSource

Module `Hardcaml.Cyclesim`Source