package diffast-langs-verilog

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Verilog parser plugin for Diff/AST

Install 

dune-project
 Dependency

github.com Readme Edit opam file Versions (5)

Authors

  1. C
    Codinuum <codinuum@me.com>
  2. M
    Masatomo Hashimoto <m.hashimoto@stair.center>

Maintainers

  1. C
    Codinuum <codinuum@me.com>
  2. M
    Masatomo Hashimoto <m.hashimoto@stair.center>

Sources

v0.4.tar.gz
sha256=f58dc5326c1698e22b84e3b808e6008228071f5796cda65433106e0d42c0dad5
sha512=8e451ab99433ef479c7d3aa0396bab6650894a2c3282e72cc65014d61f59dde578020d4bc9d423045e66d1d4592b58e877d7bd830788aeb96e5fa4ba534b4b78

doc/src/diffast-langs-verilog.base/v_lib_base.ml.html

Source file v_lib_base.ml

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(*
   Copyright 2012-2025 Codinuum Software Lab <https://codinuum.com>

   Licensed under the Apache License, Version 2.0 (the "License");
   you may not use this file except in compliance with the License.
   You may obtain a copy of the License at

       http://www.apache.org/licenses/LICENSE-2.0

   Unless required by applicable law or agreed to in writing, software
   distributed under the License is distributed on an "AS IS" BASIS,
   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   See the License for the specific language governing permissions and
   limitations under the License.
*)
(* verilog/v_lib_base.ml *)

module Xprint = Diffast_misc.Xprint
module Sourcecode = Diffast_core.Sourcecode
module Lang_base = Diffast_core.Lang_base
module Common = Verilog_parsing.Common
module Lib = Verilog_parsing.Lib


module Label = V_label

module Tree      = Sourcecode.Tree (Label)
module Fact      = V_fact.F (Label)


class tree_builder options =
  let _parser = new Lib.parser_c in
  object
    inherit Lang_base.tree_builder

    method from_xnode = Tree.of_xnode options

    method build_tree file =
      Xprint.verbose options#verbose_flag "parsing \"%s\"...\n%!" file#path;
      _parser#add_search_path file#dirname;
      try
        let ast = _parser#parse_file file in
        let tree = V_tree.of_ast options ast in
        tree#set_source_info file;
        tree#set_parser_name Sverilog.parser_name;
        tree
      with
        Common.Parse_error(head, msg) ->
          raise (Lang_base.Parse_error (Printf.sprintf "[Verilog]%s" head, msg))

    method! extra_source_files = _parser#extra_source_files

    initializer
      _parser#_set_verbose_flag options#verbose_flag;
      _parser#_set_keep_going_flag options#keep_going_flag;
      _parser#set_search_path_list options#search_path_list;

      if options#verilog_ignore_include_flag then
        _parser#set_ignore_include_flag
      else
        _parser#clear_ignore_include_flag

  end