package diffast-langs-verilog

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Module V_label.GateSource

include module type of struct include Ls.Gate end
Sourcetype t = Verilog_parsing.Labels.Gate.t =
  1. | Gate of Verilog_parsing.Labels.gate
  2. | And
  3. | Buf
  4. | Nand
  5. | Nor
  6. | Not
  7. | Or
  8. | Xnor
  9. | Xor
  10. | Anonymous
Sourceval to_string : t -> string
Sourceval to_simple_string : t -> string
Sourceval gate_to_tag : Verilog_parsing.Labels.gate -> string
Sourceval to_tag : t -> string * 'a list
Sourceval anonymize : t -> t
Sourceval gate_to_short_string : Ls.gate -> string
Sourceval to_short_string : t -> string