package diffast-langs-verilog
Source file verilog_base.ml
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16(* generated by dune *) (** @canonical Verilog_base.V_fact *) module V_fact = Verilog_base__V_fact (** @canonical Verilog_base.V_label *) module V_label = Verilog_base__V_label (** @canonical Verilog_base.V_lib_base *) module V_lib_base = Verilog_base__V_lib_base (** @canonical Verilog_base.V_tree *) module V_tree = Verilog_base__V_tree (** @canonical Verilog_base.V_unparsing *) module V_unparsing = Verilog_base__V_unparsing